📄 hw2.map.rpt
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+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+----------------+
+----------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+-----------------------------------------------------+---------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+-----------------------------------------------------+---------------------+------------------------+
; bm2:inst|comb_2010 ; pin233_en ; yes ;
; bm2:inst|comb_2016 ; pin233_en ; yes ;
; bm2:inst|comb_2022 ; pin233_en ; yes ;
; bm2:inst|comb_2028 ; pin233_en ; yes ;
; bm2:inst|comb_2034 ; pin233_en ; yes ;
; bm2:inst|comb_2040 ; pin233_en ; yes ;
; bm2:inst|comb_2046 ; pin233_en ; yes ;
; bm2:inst|comb_2052 ; pin233_en ; yes ;
; bm2:inst|comb_2058 ; pin233_en ; yes ;
; bm2:inst|comb_2064 ; pin233_en ; yes ;
; bm2:inst|comb_2070 ; pin233_en ; yes ;
; bm2:inst|comb_2076 ; pin233_en ; yes ;
; bm2:inst|comb_2082 ; pin233_en ; yes ;
; bm2:inst|comb_2088 ; pin233_en ; yes ;
; bm2:inst|comb_2094 ; pin233_en ; yes ;
; bm2:inst|comb_2100 ; pin233_en ; yes ;
; bm2:inst|comb_2106 ; pin233_en ; yes ;
; bm2:inst|comb_2112 ; pin233_en ; yes ;
; bm2:inst|comb_2118 ; pin233_en ; yes ;
; bm2:inst|comb_2124 ; pin233_en ; yes ;
; bm2:inst|comb_2130 ; pin233_en ; yes ;
; bm2:inst|comb_2136 ; pin233_en ; yes ;
; bm2:inst|comb_2142 ; pin233_en ; yes ;
; bm2:inst|comb_2148 ; pin233_en ; yes ;
; bm2:inst|comb_2154 ; pin233_en ; yes ;
; bm2:inst|comb_2160 ; pin233_en ; yes ;
; bm2:inst|comb_2166 ; pin233_en ; yes ;
; bm2:inst|comb_2172 ; pin233_en ; yes ;
; bm2:inst|comb_2178 ; pin233_en ; yes ;
; bm2:inst|comb_2184 ; pin233_en ; yes ;
; bm2:inst|comb_2190 ; pin233_en ; yes ;
; bm2:inst|comb_2196 ; pin233_en ; yes ;
; bm2:inst|comb_2202 ; pin233_en ; yes ;
; bm2:inst|comb_2208 ; pin233_en ; yes ;
; Number of user-specified and inferred latches = 34 ; ; ;
+-----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 73 ;
; Number of registers using Synchronous Clear ; 7 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 34 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |hw2|bm2:inst|cnt1[1] ;
; 5:1 ; 7 bits ; 21 LEs ; 7 LEs ; 14 LEs ; Yes ; |hw2|bm2:inst|cnt2[0] ;
; 10:1 ; 3 bits ; 18 LEs ; 6 LEs ; 12 LEs ; No ; |hw2|bm2:inst|Selector0 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
Info: Processing started: Thu Mar 26 12:57:40 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off hw2 -c hw2
Info: Found 1 design units, including 1 entities, in source file hw2.bdf
Info: Found entity 1: hw2
Info: Found 2 design units, including 1 entities, in source file bm2.vhd
Info: Found design unit 1: bm2-one
Info: Found entity 1: bm2
Info: Found 2 design units, including 1 entities, in source file fenpin.vhd
Info: Found design unit 1: fenpin-one
Info: Found entity 1: fenpin
Info: Found 2 design units, including 1 entities, in source file zb.vhd
Info: Found design unit 1: zb-one
Info: Found entity 1: zb
Info: Elaborating entity "hw2" for the top level hierarchy
Info: Elaborating entity "zb" for hierarchy "zb:inst2"
Warning (10631): VHDL Process Statement warning at zb.vhd(19): inferring latch(es) for signal or variable "zb1", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at zb.vhd(19): inferred latch for "zb1"
Info: Elaborating entity "bm2" for hierarchy "bm2:inst"
Warning (10631): VHDL Process Statement warning at bm2.vhd(338): inferring latch(es) for signal or variable "current_state", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for "current_state.st33"
Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for "current_state.st32"
Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for "current_state.st31"
Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for "current_state.st30"
Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for "current_state.st29"
Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for "current_state.st28"
Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for "current_state.st27"
Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for "current_state.st26"
Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for "current_state.st25"
Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for "current_state.st24"
Info (10041): Verilog HDL or VHDL info at bm2.vhd(338): inferred latch for "current_state.st23"
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