an introduction to delta sigma converters.mht

Intro to Delta Sigma and PWM

<P>
<CENTER><IMG height=3D200=20
alt=3D"Equivalent Circuit Block Diagram for Noise Considerations"=20
src=3D"http://www.beis.de/Elektronik/DeltaSigma/DeltaSigmaNoiseBlockDiagr=
am.GIF"=20
width=3D439 align=3Dbottom border=3D0 NATURALSIZEFLAG=3D"3"></CENTER>
<P></P>
<P>
<CENTER><B>Figure 9 - Equivalent Circuit Block Diagram for Noise=20
Considerations</B></CENTER>
<P></P>
<P>It can be regarded this way because a) the output of the modulator =
still=20
contains the average input value and b) the (mainly randomly) "jumping"=20
bitstream is a kind of noise - white noise to be more precise. Think =
about this=20
or just believe me.</P>
<P>The frequency responses from both inputs to the bitstream output =
result from=20
the integrator being</P>
<UL>
  <LI>in the forward path of the loop for the analogue input so that a =
low-pass=20
  filter characteristic must result and=20
  <LI>in the feed-back path of the loop for the noise input so that a =
high-pass=20
  filter characteristic must result </LI></UL>
<P>We can compute both frequency responses which for 1<SUP>st</SUP> and=20
2<SUP>nd</SUP> order modulators look like this:</P>
<P>
<CENTER><IMG height=3D248 alt=3D"Frequency Responses Causing Noise =
Shaping"=20
src=3D"http://www.beis.de/Elektronik/DeltaSigma/DeltaSigmaFrequ.GIF" =
width=3D404=20
align=3Dbottom border=3D0 NATURALSIZEFLAG=3D"3"></CENTER>
<P></P>
<P>
<CENTER><B>Figure 10 - Frequency Responses Causing Noise =
Shaping</B></CENTER>
<P></P>
<P>In the lower frequency band the desired input signals are passed and =
changed=20
little, while the noise is suppressed to a great extent. With higher =
order=20
modulators the noise is even more suppressed. This is called "<B>noise=20
shaping</B>". And this is the reason why higher order modulators produce =
less=20
output noise.</P>
<P>If you now start to compute noise figures depending on the modulators =
order=20
and the oversampling rate you will get the SNR-diagram shown in Figure =
8. For=20
further details refer to the Intersil application note "<A=20
href=3D"http://www.intersil.com/data/an/AN9504.pdf" target=3D_blank>A =
Brief=20
Introduction to Sigma Delta Conversion</A>". (Attention: Figure 6 "SNR =
vs=20
Oversampling Ratio" is wrong. Use "my" Figure 8 instead.) I found =
another=20
interesting introduction for various kinds of A/D converters including =
delta=20
sigma:The Rane company: <A href=3D"http://www.rane.com/note137.html"=20
target=3D_blank>Digital Dharma of Audio A/D Converters</A>.</P>
<H3>Decimation</H3>
<P>I did not mention the term "decimation" yet at all because it is =
neither a=20
process nor is it mystic - it's trivial. It is required when a =
bitstream, e.g.=20
the output of an analogue modulator, shall be converted to a PCM =
signal.</P>
<P>The core statement is: <I>Without losing any information in =
oversampled=20
signals as many samples can be left out until the signal is not =
oversampled any=20
more</I>. (That's why it is called "oversampled"!)</P>
<P>
<CENTER><IMG height=3D115=20
src=3D"http://www.beis.de/Elektronik/DeltaSigma/PCM-ADC.GIF" width=3D472 =

align=3Dbottom border=3D0 NATURALSIZEFLAG=3D"3"></CENTER>
<P></P>
<P>
<CENTER><B>Figure 11 - Delta Sigma based ADC with PCM =
Output</B></CENTER>
<P></P>
<P>Decimation takes place in delta sigma converters at the output of the =
digital=20
low-pass filter. The bitstream is clocked with the sampling rate times =
the=20
oversampling rate (e.g. 64 times the sample rate), and so the output of =
the=20
digital low pass is clocked with the oversampling rate, too. But the =
sample rate=20
clock (twice the input bandwidth) is required at the digital output =
only. Here=20
decimation comes up: For an oversampling rate of e.g. 64 every =
64<SUP>th</SUP>=20
sample is taken, all others are discarded. This is possible because the =
signal=20
is bandwidth limited by the digital low pass filter correspondingly. =
Quite=20
simple - isn't it?</P>
<H3><A name=3DMultiBit></A>Multi-Bit Converter</H3>
<P>The feedback from the 1-Bit DAC to the block "Difference" introduces =
a lot of=20
noise in an analogue modulator like in <A=20
href=3D"http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma.html#BlockDia=
g1stA">Figure=20
2</A>. It is possible to reduce this noise by not only using one, but =
several=20
bits instead. The comparator of Figure 2, which actually operates as a =
1-bit=20
ADC, is replaced by an N-bit ADC, and the latch and the DAC must be N =
bit wide,=20
too:</P>
<P>
<CENTER><IMG height=3D208=20
src=3D"http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma1NBlockDiagram.=
GIF"=20
width=3D677 align=3Dbottom border=3D0 NATURALSIZEFLAG=3D"3"></CENTER>
<P></P>
<P>
<CENTER><B>Figure 12 - Delta-Sigma based Multi-Bit ADC with PCM=20
Output</B></CENTER>
<P></P>
<P>The modulator's output signal will also become N bit wide and thus =
can no=20
longer be called "bitstream", but it is as suitable to be converted to a =
PCM=20
signal as the single bit wide bitstream is. Because less noise is =
introduced,=20
the oversampling rate may be reduced or the PCM output's width can be =
increased.=20
This is why in practice multi-bit modulators are normally used in ADCs. =
Note:=20
The modulator's internal signal width "N" is usually a few bits =
only.</P>
<H3><A name=3DBitstreamMath></A>Mathematical Operations with Bitstream=20
Signals</H3>
<P>Doing mathematical operations like adding two signals or multiplying =
a signal=20
with a constant (or with another signal) or even other linear or =
nonlinear=20
operations like filtering is easy to understand for PCM signals. But how =
to do=20
this with bitstream signals? Any non-trivial mathematical operation on =
quantized=20
signals significantly affects the lower significant data bits but a =
bitstream=20
has no LSBits. The input is a one-bit signal and the output has to be a =
one-bit=20
signal, too!</P>
<P>The <B>first approach</B> is obvious, but not very smart: Convert the =

bitstream to a PCM signal, do the desired operation(s) and convert the =
result=20
back to a bitstream:</P>
<P>
<CENTER><IMG height=3D125=20
src=3D"http://www.beis.de/Elektronik/DeltaSigma/DSP-PCM.GIF" width=3D755 =

align=3Dbottom border=3D0 NATURALSIZEFLAG=3D"3"></CENTER>
<P></P>
<P>
<CENTER><B>Figure 13 - Bitstream Operations using the PCM =
Detour</B></CENTER>
<P></P>
<P>In practice, the digital signal processor in this block diagram may =
be a=20
simple adder or multplier circuit. Also, there must not necessarily be a =
second=20
bitstream input.</P>
<P>This "less smart" method takes one digital filter/decimator per input =
signal=20
and one digital modulator for the output signal. Another issue of this =
method is=20
the PCM clock (or sample rate resp.) which has to be introduced: A =
bitstream has=20
no other sample rate than its bitstream clock, so that an arbitrary PCM =
sample=20
rate ought to be chosen. This causes a loss of signal bandwidth due to =
the=20
required digital filter and decimator.</P>
<P>The <B>second approach</B> is a more clever way to do it: For =
example, what=20
happens if you want to just add two bitstream signals (e.g., mix two =
audio=20
signals) and simply add the bits of both bitstreams? You'll get a 2-bit =
signal=20
(PCM, this not what you need), but its average level still represents =
the sum of=20
the original input signals. We "only" need to convert this 2-bit PCM =
signal into=20
a 1-bit one. Just one digital modulator is needed for that, not more, =
not=20
less:</P>
<P>
<CENTER><IMG height=3D112=20
src=3D"http://www.beis.de/Elektronik/DeltaSigma/BitstreamAdd.GIF" =
width=3D515=20
align=3Dbottom border=3D0 NATURALSIZEFLAG=3D"3"></CENTER>
<P></P>
<P>
<CENTER><B>Figure 14 - Adding two Bitstream Signals</B></CENTER>
<P></P>
<P>To understand this, we need a closer look on the digital modulator I=20
explained in <A=20
href=3D"http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma.html#BlockDia=
g1stD">Figure=20
3</A>. What I did not point out there is the fact that</P>
<UL>
  <LI>the PCM-Signal "Digital In" has a low clock rate (the PCM sample =
rate)=20
  while=20
  <LI>the output of the 1-Bit DDC has the bitstream's clock rate, e.g. =
64 times=20
  the PCM signal's clock rate. </LI></UL>
<P>Actually, the subtractor "Difference" in Figure 3 operates at the =
bitstream's=20
clock rate and subtracts the 1-Bit DDC's PCM output signal from another, =
slowly=20
clocked PCM signal. This subtractor is also able to subtract two PCM =
signals,=20
both with the higher clock rate, of course. While the 2-bit sum of both=20
bitstreams is not a usual PCM signal that represents the actual signal =
value at=20
any time, it still can be viewed as a usable PCM signal for the digital=20
modulator because it is sufficient when its temporal average value is =
correct.=20
This, BTW, is very similar to the situation with the multi-bit signals =
in=20
multi-bit converters.</P>
<P>Because the digital modulator's signal with needs only to be as wide =
as its=20
digital input, in this example the circuit diagram for the digital =
modulator=20
becomes quite simple as the bitstream adder's output signal is only 2 =
bit=20
wide.</P>
<P>The <B>general solution</B> for mathematics with bitstreams looks =
like=20
this:</P>
<P>
<CENTER><IMG height=3D141=20
src=3D"http://www.beis.de/Elektronik/DeltaSigma/DSP-PPM.GIF" width=3D755 =

align=3Dbottom border=3D0 NATURALSIZEFLAG=3D"3"></CENTER>
<P></P>
<P>
<CENTER><B>Figure 15 - Bitstream Operations Directly on Bitstream=20
Signals</B></CENTER>
<P></P>
<UL>
  <LI>Take one or more bitstream(s) and convert them into PCM signals by =
just=20
  manifolding the single bitstream bit for each PCM data bit (that's =
exactly=20
  what the <A=20
  =
href=3D"http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma.html#1BitDDC"=
>1-Bit=20
  DDC I described above</A> does).=20
  <LI>Do any mathematical operation (=3D digital signal process) you =
want on this=20
  PCM signal - add, multiply, filter, nonliner operations or whatsoever. =
The=20
  algorithms to be applied are the same ones as in any other DSP =
application.=20
  You only need a sufficient signal width (number of bits for the PCM =
signal) in=20
  order to achieve the signal quality you aim, and for simple operations =
this=20
  width may be 2 bits or just 1. Keep in mind that these operations take =
place=20
  with the bitstream's clock rate.=20
  <LI>Use a digital modulator with the same input signal width as your=20
  mathematical operation provides to re-convert the "semi-PCM"-signal =
(=3D=20
  "multi-bit Delta Sigma modulated data stream") to a single bit =
bitstream.=20
</LI></UL>
<P>That's it. This "smart" solution takes no digital filter/decimator =
per input=20
signal and only one (often quite simple) digital modulator for the =
output=20
signal.</P>
<H3>Additional Thoughts and Cognitions</H3>
<P><B>Alias effects</B>: Delta sigma converters must run with sampling=20
frequencies much higher than twice the maximum signal frequency (which =
is the=20
minimum sample frequency of e.g. digital outputs). This has a very =