an introduction to delta sigma converters.mht

Intro to Delta Sigma and PWM

    <TD>-10&nbsp;V to +10&nbsp;V</TD></TR></TBODY></TABLE></P>
<P>Likewise, in the digital modulator the following input ranges are=20
obtained:</P>
<P>
<TABLE cellSpacing=3D0 cellPadding=3D3 border=3D1>
  <TBODY>
  <TR>
    <TD>DRef-</TD>
    <TD>DRef+</TD>
    <TD>Input Range</TD>
    <TD>Type</TD></TR>
  <TR>
    <TD>00&nbsp;(hex)</TD>
    <TD>FF&nbsp;(hex)</TD>
    <TD>00&nbsp;(hex) to FF&nbsp;(hex)</TD>
    <TD>Unsigned Binary Byte</TD></TR>
  <TR>
    <TD>8000&nbsp;(hex)</TD>
    <TD>7FFF&nbsp;(hex)</TD>
    <TD>-32768 to +32767 (decimal)</TD>
    <TD>Signed Binary 16 Bit</TD></TR></TBODY></TABLE></P>
<P><A name=3D1BitDDC></A>As a circuit diagram, the 1-Bit DDC may be as =
simple as a=20
manifold of the input signal to all output data bits:</P>
<P>
<CENTER><IMG height=3D112=20
src=3D"http://www.beis.de/Elektronik/DeltaSigma/1BitDDC.GIF" width=3D656 =

align=3Dbottom border=3D0 NATURALSIZEFLAG=3D"3"></CENTER>
<P></P>
<P>
<CENTER><B>Figure 4 - Two simple 1-Bit DDCs<BR></B>Left: Unsigned (0 to=20
2<SUP>n</SUP>), Right: Signed (-2<SUP>n-1</SUP> to =
+2<SUP>n-1</SUP>-1)</CENTER>
<P></P>
<P>The <B>first order modulator's signal diagrams</B> look like this =
(analogue=20
version):</P>
<P>
<CENTER><IMG height=3D648 alt=3D"Signals within a First Order Analog =
Modulator"=20
src=3D"http://www.beis.de/Elektronik/DeltaSigma/DeltaSigmaSinus.gif" =
width=3D763=20
align=3Dbottom border=3D0 NATURALSIZEFLAG=3D"3"></CENTER>
<P></P>
<P>
<CENTER><B>Figure 5 - Signals within a First Order Analogue=20
Modulator</B></CENTER>
<P></P>
<P>Note that in this example the clock rate, which here is also the =
sample rate,=20
is 64 times higher than the frequency of the input signal. Conventional=20
converters require a sample rate of more than twice the highest input =
frequency.=20
Delta sigma converters require much more in order to produce a =
sufficient number=20
of bitstream pulses. It is obvious: The more bitstream pulses are =
produced the=20
better is the approximation of the input signal by the average =
bitstream.</P>
<P>Once again: <B>The average (low pass filtered) bitstream never(!) =
exactly=20
represents the input signal. It is always(!) superimposed by some kind =
of=20
noise.</B></P>
<P>One way to reduce this noise is to further increase the clock rate. =
Due to=20
the sampling theorem the sampling rate must be higher than twice the =
maximum=20
input frequency. Any further increase is called "<B>oversampling =
rate</B>".=20
Example: Assume an audio signal with a bandwidth of up to 20&nbsp;kHz =
(and=20
probably slightly more). A typical sampling rate (for DAT etc.) is =
48&nbsp;kHz.=20
In a typical delta sigma converter the clock frequency (which usually is =
also=20
the sample rate) will be 64 x 48&nbsp;kHz&nbsp;=3D&nbsp;3072&nbsp;kHz. =
This is=20
equal to an oversampling rate of 64. In the example above (Figure 4) the =
clock=20
frequency is 64 times higher than the frequency of the input signal. =
This means=20
that the oversampling rate must be less than 32 for the given input =
frequency.=20
(I don't know why only oversampling rates in the form of 2<SUP>n</SUP> =
are=20
actually implemented. In my opinion any other form of this factor should =
be=20
possible, too.)</P>
<P>Another - and better - way to reduce the noise is to use a higher =
order delta=20
sigma modulator. Bitstreams produced by higher order modulators produce =
less=20
noise at the low pass filter outputs. Normally this noise is random. =
First order=20
modulators show some strong frequencies in the power spectrum =
(non-random noise=20
or residual tones), which is disadvantgeous. If the input signal is =
close to the=20
limits of the input range this effect is worst with first order =
modulators. If=20
you want to know more about this refer to "<A=20
href=3D"http://www.beis.de/Elektronik/DeltaSigma/1stOrderDisadvantages.ht=
ml"=20
target=3D_blank>First Order Delta Sigma Modulator =
Disadvantages</A>".</P>
<P>A <B>second order delta sigma modulator</B> may look like this:</P>
<P>
<CENTER><IMG height=3D200=20
alt=3D"Block Diagram of a Second Order Analog Delta Sigma Modulator"=20
src=3D"http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma2BlockDiagram.G=
IF"=20
width=3D711 align=3Dbottom border=3D0 NATURALSIZEFLAG=3D"3"></CENTER>
<P></P>
<P>
<CENTER><B>Figure 6 - Block Diagram of a Second Order Analogue Delta =
Sigma=20
Modulator</B></CENTER>
<P></P>
<P>The bitstream of such a modulator is much closer to the ideal pulse=20
proportion signal than the one above so that<BR>- either the input =
signal=20
bandwidth may be higher,<BR>- or the clock rate may be lower,<BR>- or =
the output=20
precision is increased (less noise)<BR>whatever you want to achieve.=20
Additionally "non-random noise" is avoided to a great extent.</P>
<P><B>Delta sigma modulators of orders higher than 2</B> are possible to =

construct but they cannot simply be made by adding further stages as =
above. The=20
reason is that the phase turn caused by more than two integrators will =
make the=20
system unstable. Low pass filters are used instead. Delta sigma ADCs for =
audio=20
applications typically use 5th order modulators and, as mentioned above, =

oversampling rates of 64. The architecture may look different, e.g. =
2-bit DACs,=20
but the basic principle of operation remains the same.</P>
<P>5th order and an oversampling rate of 64 - why that much?</P>
<H3>A Short Introduction to ADC and DAC Noise</H3>
<P>As already mentioned within the average (low pass filtered) bitstream =
noise=20
always remains. The amount of noise depends on a) the oversampling rate =
and b)=20
the order of the modulator that produced the bitstream. Obviously it =
will not=20
make sense to provide a 16 bit output to an ADC where the low 8 bit =
randomly=20
change due to the remaining noise.</P>
<P>You may have heard that signals converted by ADCs suffer from =
<B>quantization=20
noise</B>. Where does this come from? If a DC-voltage is applied to an =
ADC the=20
output remains stable. It represents the input voltage more or less =
precisely,=20
but without noise. So, where is there noise?</P>
<P>It's because the conversion is "more or less precisely" only. A =
constant=20
error in a DC measurement corresponds to a random error or white noise =
(=3D noise=20
with equal distribution over its spectrum) in a conversion with a =
varying signal=20
(AC). A digital n bit signal can only settle to 2<SUP>n</SUP> values but =
the=20
analogue input signal may have any value. It is this difference between =
the=20
analogue value and its digital representation which causes the problem. =
This is=20
called the quantization noise. In the example below a 4 bit ADC (=3D =
2<SUP>4</SUP>=20
=3D 16 quantization levels) is assumed:<BR></P>
<P>
<CENTER><IMG height=3D292=20
alt=3D"Quantization Noise in Digital (PCM) Systems - Sinewave"=20
src=3D"http://www.beis.de/Elektronik/DeltaSigma/ADCSinus.GIF" =
width=3D670=20
align=3Dbottom border=3D0 NATURALSIZEFLAG=3D"3"></CENTER>
<P></P>
<P>
<CENTER><IMG height=3D267=20
alt=3D"Quantization Noise in Digital (PCM) Systems - Audio Signal"=20
src=3D"http://www.beis.de/Elektronik/DeltaSigma/ADCSound.GIF" =
width=3D670=20
align=3Dbottom border=3D0 NATURALSIZEFLAG=3D"3"></CENTER>
<P></P>
<P>
<CENTER><B>Figure 7 - Quantization Noise in Digital (PCM) Systems, =
Sinewave and=20
Audio Signal</B></CENTER>
<P></P>
<P>One can see that more quantization levels reduce the remaining =
quantization=20
noise. Using an ideal ADC with n bits the signal to noise ratio (SNR) =
is:<BR>n *=20
6.02 + 1.76 [dB] (or 2<SUP>n</SUP> * Sqr(3/2)) referred to a full scale =
sine=20
wave signal or<BR>n * 6.02 + 10.79 [dB] (or 2<SUP>n</SUP> * Sqr(12)) =
referred to=20
the maximum peak-to-peak output voltage.<BR>Thus for an ideal 16 bit ADC =
the SNR=20
achievable is 98.1 dB and the SNR for the 4-bit signal above is 25.8 =
dB.</P>
<H3>The Conversion Noise of Delta Sigma Converters</H3>
<P>Please note that <B>conversion noise</B> and not quantization noise =
is=20
discussed here. Conversion noise appears already in the bitstream. =
Quantization=20
noise appears only when signals are represented digitally. As mentioned =
above=20
the amount of conversion noise depends on the oversampling rate and the =
order of=20
the modulator. It can be expressed mathematically and results in the =
following=20
graphs for delta sigma modulators with orders of 0, 1, 2, 3, 4 and =
5:</P>
<P>
<CENTER><IMG height=3D277 alt=3D"Delta Sigma Conversion Noise"=20
src=3D"http://www.beis.de/Elektronik/DeltaSigma/DeltaSigmaSNR.GIF" =
width=3D393=20
align=3Dbottom border=3D0 NATURALSIZEFLAG=3D"3"></CENTER>
<P></P>
<P>
<CENTER><B>Figure 8 - Delta Sigma Conversion Noise<BR>SNR vs. =
Oversampling Rate=20
and Modulator Order (0&nbsp;-&nbsp;5)</B></CENTER>
<P></P>
<P>Now you can figure out which parameters (oversampling rate and order) =
of the=20
modulator are required to obtain which noise. If a signal must be =
quantized, you=20
may decide either the quantization noise or the conversion noise to be =
the=20
bottle neck of the overall noise performance. In case that both shall =
have an=20
equal effect, the overall SNR is reduced by 3 dB related to each of the =
noise=20
portions.</P>
<P>Example: A 16 bit ADC, realized with a 3rd order modulator and a 64 =
fold=20
oversampling rate would add -106 dB of conversion noise to the -98 dB=20
quantization noise, so that quantization noise is prevailing and will be =

deteriorated by less than 1&nbsp;dB only.</P>
<P>These SNR-figures are valid only for ideal converters. As so often in =

practice, the actually yielded SNR amongst others depends on the =
conversion=20
speed and the IC-technology.</P>
<P>High quality ADCs for audio applications provide 24 output bits. They =
use 5th=20
order modulators so that the conversion noise could be theoretically at =
-160 dB.=20
The quantization noise of a 24 bit converter could become better than =
-147 dB.=20
Real good ADC achieve "just" 120 dB SNR (19.6 effective bits) due to the =

non-ideal operation of the modulator (Example: <A=20
href=3D"http://www.cirrus.com/en/products/pro/detail/P1024.html"=20
target=3D_blank>Cirrus Logic CS5381</A>). Nevertheless 120&nbsp;dB is a =
fantastic=20
value: 10<SUP>6</SUP> or 1:1,000,000 is close to the dynamic range of =
the human=20
ear! Another 24 bit delta sigma ADC I know yields an SNR of 140&nbsp;dB, =
but=20
with an output rate of 7&nbsp;Hz "only" (<A=20
href=3D"http://www.linear.com/pc/productDetail.do?navId=3DH0,C1,C1155,C10=
01,C1152,P1771"=20
target=3D_blank>Linear Technology LTC2440</A>).</P>
<H3>The "Noise View" on Delta Sigma Converters</H3>
<P>The "conventional" way to explain Delta Sigma Converters is to look =
at the=20
noise generated within the modulator and then to figure out how much =
noise=20
remains after the low pass filter. This did not help me to understand =
what's=20
going on inside the converters and so I disregarded this kind of view as =
yet.=20
Let us have a short look on the mathematical background even though:</P>
<P>I want to describe the frequency response of a 1<SUP>st</SUP> order =
modulator=20
like the one in Figure 2. But how to do it, when there are such strange, =

non-linear elements like comparators and latches in it? It took me a =
while to=20
accept: The comparator/latch combination can be taken as an adder of =
noise to=20
the output signal of the integrator, so a modulator block diagram like =
this=20
results:</P>