fenpin1hz.vhd

来自「多功能电子钟」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpin1Hz is
port( clk_in : in std_logic;
      clk_out : out std_logic);
end entity;
architecture behav of fenpin1Hz is
signal tout : integer range 0 to 25000000;
signal clk: std_logic;
begin
  process(clk_in)
  begin
    if rising_edge(clk_in) then
      if tout=24999999 then   --此处tout＝n，输出结果即为clk_in的(n+1)×2倍分频
        tout<=0;         --如此处的n=3，则输出clk_out为clk_in的8分频
        clk<=not clk;
      else
        tout<=tout+1;
      end if;
    end if;
  end process;
clk_out<=clk;
end behav;