fenpin1hz.tan.qmsg

多功能电子钟

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_in " "Info: Assuming node \"clk_in\" is an undefined clock" {  } { { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 5 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk_in" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_in register tout\[0\] register tout\[21\] 253.49 MHz 3.945 ns Internal " "Info: Clock \"clk_in\" has Internal fmax of 253.49 MHz between source register \"tout\[0\]\" and destination register \"tout\[21\]\" (period= 3.945 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.734 ns + Longest register register " "Info: + Longest register to register delay is 3.734 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tout\[0\] 1 REG LCFF_X63_Y22_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X63_Y22_N9; Fanout = 3; REG Node = 'tout\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { tout[0] } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.318 ns) + CELL(0.393 ns) 0.711 ns Add0~301 2 COMB LCCOMB_X63_Y22_N8 2 " "Info: 2: + IC(0.318 ns) + CELL(0.393 ns) = 0.711 ns; Loc. = LCCOMB_X63_Y22_N8; Fanout = 2; COMB Node = 'Add0~301'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.711 ns" { tout[0] Add0~301 } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.782 ns Add0~303 3 COMB LCCOMB_X63_Y22_N10 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.782 ns; Loc. = LCCOMB_X63_Y22_N10; Fanout = 2; COMB Node = 'Add0~303'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~301 Add0~303 } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.853 ns Add0~305 4 COMB LCCOMB_X63_Y22_N12 2 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 0.853 ns; Loc. = LCCOMB_X63_Y22_N12; Fanout = 2; COMB Node = 'Add0~305'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~303 Add0~305 } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 1.012 ns Add0~307 5 COMB LCCOMB_X63_Y22_N14 2 " "Info: 5: + IC(0.000 ns) + CELL(0.159 ns) = 1.012 ns; Loc. = LCCOMB_X63_Y22_N14; Fanout = 2; COMB Node = 'Add0~307'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.159 ns" { Add0~305 Add0~307 } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.083 ns Add0~309 6 COMB LCCOMB_X63_Y22_N16 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.083 ns; Loc. = LCCOMB_X63_Y22_N16; Fanout = 2; COMB Node = 'Add0~309'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~307 Add0~309 } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.154 ns Add0~311 7 COMB LCCOMB_X63_Y22_N18 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.154 ns; Loc. = LCCOMB_X63_Y22_N18; Fanout = 2; COMB Node = 'Add0~311'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~309 Add0~311 } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.225 ns Add0~313 8 COMB LCCOMB_X63_Y22_N20 2 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.225 ns; Loc. = LCCOMB_X63_Y22_N20; Fanout = 2; COMB Node = 'Add0~313'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~311 Add0~313 } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.296 ns Add0~315 9 COMB LCCOMB_X63_Y22_N22 2 " "Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 1.296 ns; Loc. = LCCOMB_X63_Y22_N22; Fanout = 2; COMB Node = 'Add0~315'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~313 Add0~315 } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.367 ns Add0~317 10 COMB LCCOMB_X63_Y22_N24 2 " "Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 1.367 ns; Loc. = LCCOMB_X63_Y22_N24; Fanout = 2; COMB Node = 'Add0~317'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~315 Add0~317 } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.438 ns Add0~319 11 COMB LCCOMB_X63_Y22_N26 2 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 1.438 ns; Loc. = LCCOMB_X63_Y22_N26; Fanout = 2; COMB Node = 'Add0~319'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~317 Add0~319 } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.509 ns Add0~321 12 COMB LCCOMB_X63_Y22_N28 2 " "Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 1.509 ns; Loc. = LCCOMB_X63_Y22_N28; Fanout = 2; COMB Node = 'Add0~321'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~319 Add0~321 } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.146 ns) 1.655 ns Add0~323 13 COMB LCCOMB_X63_Y22_N30 2 " "Info: 13: + IC(0.000 ns) + CELL(0.146 ns) = 1.655 ns; Loc. = LCCOMB_X63_Y22_N30; Fanout = 2; COMB Node = 'Add0~323'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.146 ns" { Add0~321 Add0~323 } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.726 ns Add0~325 14 COMB LCCOMB_X63_Y21_N0 2 " "Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 1.726 ns; Loc. = LCCOMB_X63_Y21_N0; Fanout = 2; COMB Node = 'Add0~325'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~323 Add0~325 } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.797 ns Add0~327 15 COMB LCCOMB_X63_Y21_N2 2 " "Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 1.797 ns; Loc. = LCCOMB_X63_Y21_N2; Fanout = 2; COMB Node = 'Add0~327'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~325 Add0~327 } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.868 ns Add0~329 16 COMB LCCOMB_X63_Y21_N4 2 " "Info: 16: + IC(0.000 ns) + CELL(0.071 ns) = 1.868 ns; Loc. = LCCOMB_X63_Y21_N4; Fanout = 2; COMB Node = 'Add0~329'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~327 Add0~329 } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.939 ns Add0~331 17 COMB LCCOMB_X63_Y21_N6 2 " "Info: 17: + IC(0.000 ns) + CELL(0.071 ns) = 1.939 ns; Loc. = LCCOMB_X63_Y21_N6; Fanout = 2; COMB Node = 'Add0~331'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~329 Add0~331 } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.010 ns Add0~333 18 COMB LCCOMB_X63_Y21_N8 2 " "Info: 18: + IC(0.000 ns) + CELL(0.071 ns) = 2.010 ns; Loc. = LCCOMB_X63_Y21_N8; Fanout = 2; COMB Node = 'Add0~333'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~331 Add0~333 } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.081 ns Add0~335 19 COMB LCCOMB_X63_Y21_N10 2 " "Info: 19: + IC(0.000 ns) + CELL(0.071 ns) = 2.081 ns; Loc. = LCCOMB_X63_Y21_N10; Fanout = 2; COMB Node = 'Add0~335'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~333 Add0~335 } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.152 ns Add0~337 20 COMB LCCOMB_X63_Y21_N12 2 " "Info: 20: + IC(0.000 ns) + CELL(0.071 ns) = 2.152 ns; Loc. = LCCOMB_X63_Y21_N12; Fanout = 2; COMB Node = 'Add0~337'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~335 Add0~337 } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 2.311 ns Add0~339 21 COMB LCCOMB_X63_Y21_N14 2 " "Info: 21: + IC(0.000 ns) + CELL(0.159 ns) = 2.311 ns; Loc. = LCCOMB_X63_Y21_N14; Fanout = 2; COMB Node = 'Add0~339'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.159 ns" { Add0~337 Add0~339 } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.382 ns Add0~341 22 COMB LCCOMB_X63_Y21_N16 2 " "Info: 22: + IC(0.000 ns) + CELL(0.071 ns) = 2.382 ns; Loc. = LCCOMB_X63_Y21_N16; Fanout = 2; COMB Node = 'Add0~341'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~339 Add0~341 } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 2.792 ns Add0~342 23 COMB LCCOMB_X63_Y21_N18 1 " "Info: 23: + IC(0.000 ns) + CELL(0.410 ns) = 2.792 ns; Loc. = LCCOMB_X63_Y21_N18; Fanout = 1; COMB Node = 'Add0~342'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { Add0~341 Add0~342 } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.438 ns) + CELL(0.420 ns) 3.650 ns tout~233 24 COMB LCCOMB_X64_Y21_N12 1 " "Info: 24: + IC(0.438 ns) + CELL(0.420 ns) = 3.650 ns; Loc. = LCCOMB_X64_Y21_N12; Fanout = 1; COMB Node = 'tout~233'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.858 ns" { Add0~342 tout~233 } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.734 ns tout\[21\] 25 REG LCFF_X64_Y21_N13 3 " "Info: 25: + IC(0.000 ns) + CELL(0.084 ns) = 3.734 ns; Loc. = LCFF_X64_Y21_N13; Fanout = 3; REG Node = 'tout\[21\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { tout~233 tout[21] } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.978 ns ( 79.75 % ) " "Info: Total cell delay = 2.978 ns ( 79.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.756 ns ( 20.25 % ) " "Info: Total interconnect delay = 0.756 ns ( 20.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.734 ns" { tout[0] Add0~301 Add0~303 Add0~305 Add0~307 Add0~309 Add0~311 Add0~313 Add0~315 Add0~317 Add0~319 Add0~321 Add0~323 Add0~325 Add0~327 Add0~329 Add0~331 Add0~333 Add0~335 Add0~337 Add0~339 Add0~341 Add0~342 tout~233 tout[21] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.734 ns" { tout[0] Add0~301 Add0~303 Add0~305 Add0~307 Add0~309 Add0~311 Add0~313 Add0~315 Add0~317 Add0~319 Add0~321 Add0~323 Add0~325 Add0~327 Add0~329 Add0~331 Add0~333 Add0~335 Add0~337 Add0~339 Add0~341 Add0~342 tout~233 tout[21] } { 0.000ns 0.318ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.438ns 0.000ns } { 0.000ns 0.393ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.146ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.410ns 0.420ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.003 ns - Smallest " "Info: - Smallest clock skew is 0.003 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 2.685 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_in\" to destination register is 2.685 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk_in 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk_in'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk_in~clkctrl 2 COMB CLKCTRL_G3 26 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 26; COMB Node = 'clk_in~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk_in clk_in~clkctrl } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.537 ns) 2.685 ns tout\[21\] 3 REG LCFF_X64_Y21_N13 3 " "Info: 3: + IC(1.031 ns) + CELL(0.537 ns) = 2.685 ns; Loc. = LCFF_X64_Y21_N13; Fanout = 3; REG Node = 'tout\[21\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.568 ns" { clk_in~clkctrl tout[21] } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.21 % ) " "Info: Total cell delay = 1.536 ns ( 57.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.149 ns ( 42.79 % ) " "Info: Total interconnect delay = 1.149 ns ( 42.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.685 ns" { clk_in clk_in~clkctrl tout[21] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.685 ns" { clk_in clk_in~combout clk_in~clkctrl tout[21] } { 0.000ns 0.000ns 0.118ns 1.031ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 2.682 ns - Longest register " "Info: - Longest clock path from clock \"clk_in\" to source register is 2.682 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk_in 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk_in'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk_in~clkctrl 2 COMB CLKCTRL_G3 26 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 26; COMB Node = 'clk_in~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk_in clk_in~clkctrl } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.028 ns) + CELL(0.537 ns) 2.682 ns tout\[0\] 3 REG LCFF_X63_Y22_N9 3 " "Info: 3: + IC(1.028 ns) + CELL(0.537 ns) = 2.682 ns; Loc. = LCFF_X63_Y22_N9; Fanout = 3; REG Node = 'tout\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.565 ns" { clk_in~clkctrl tout[0] } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.27 % ) " "Info: Total cell delay = 1.536 ns ( 57.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.146 ns ( 42.73 % ) " "Info: Total interconnect delay = 1.146 ns ( 42.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.682 ns" { clk_in clk_in~clkctrl tout[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.682 ns" { clk_in clk_in~combout clk_in~clkctrl tout[0] } { 0.000ns 0.000ns 0.118ns 1.028ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.685 ns" { clk_in clk_in~clkctrl tout[21] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.685 ns" { clk_in clk_in~combout clk_in~clkctrl tout[21] } { 0.000ns 0.000ns 0.118ns 1.031ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.682 ns" { clk_in clk_in~clkctrl tout[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.682 ns" { clk_in clk_in~combout clk_in~clkctrl tout[0] } { 0.000ns 0.000ns 0.118ns 1.028ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.734 ns" { tout[0] Add0~301 Add0~303 Add0~305 Add0~307 Add0~309 Add0~311 Add0~313 Add0~315 Add0~317 Add0~319 Add0~321 Add0~323 Add0~325 Add0~327 Add0~329 Add0~331 Add0~333 Add0~335 Add0~337 Add0~339 Add0~341 Add0~342 tout~233 tout[21] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.734 ns" { tout[0] Add0~301 Add0~303 Add0~305 Add0~307 Add0~309 Add0~311 Add0~313 Add0~315 Add0~317 Add0~319 Add0~321 Add0~323 Add0~325 Add0~327 Add0~329 Add0~331 Add0~333 Add0~335 Add0~337 Add0~339 Add0~341 Add0~342 tout~233 tout[21] } { 0.000ns 0.318ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.438ns 0.000ns } { 0.000ns 0.393ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.146ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.410ns 0.420ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.685 ns" { clk_in clk_in~clkctrl tout[21] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.685 ns" { clk_in clk_in~combout clk_in~clkctrl tout[21] } { 0.000ns 0.000ns 0.118ns 1.031ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.682 ns" { clk_in clk_in~clkctrl tout[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.682 ns" { clk_in clk_in~combout clk_in~clkctrl tout[0] } { 0.000ns 0.000ns 0.118ns 1.028ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_in clk_out clk 6.015 ns register " "Info: tco from clock \"clk_in\" to destination pin \"clk_out\" through register \"clk\" is 6.015 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 2.685 ns + Longest register " "Info: + Longest clock path from clock \"clk_in\" to source register is 2.685 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk_in 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk_in'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk_in~clkctrl 2 COMB CLKCTRL_G3 26 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 26; COMB Node = 'clk_in~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk_in clk_in~clkctrl } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.537 ns) 2.685 ns clk 3 REG LCFF_X64_Y21_N15 2 " "Info: 3: + IC(1.031 ns) + CELL(0.537 ns) = 2.685 ns; Loc. = LCFF_X64_Y21_N15; Fanout = 2; REG Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.568 ns" { clk_in~clkctrl clk } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.21 % ) " "Info: Total cell delay = 1.536 ns ( 57.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.149 ns ( 42.79 % ) " "Info: Total interconnect delay = 1.149 ns ( 42.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.685 ns" { clk_in clk_in~clkctrl clk } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.685 ns" { clk_in clk_in~combout clk_in~clkctrl clk } { 0.000ns 0.000ns 0.118ns 1.031ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.080 ns + Longest register pin " "Info: + Longest register to pin delay is 3.080 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk 1 REG LCFF_X64_Y21_N15 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X64_Y21_N15; Fanout = 2; REG Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.468 ns) + CELL(2.612 ns) 3.080 ns clk_out 2 PIN PIN_M21 0 " "Info: 2: + IC(0.468 ns) + CELL(2.612 ns) = 3.080 ns; Loc. = PIN_M21; Fanout = 0; PIN Node = 'clk_out'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.080 ns" { clk clk_out } "NODE_NAME" } } { "fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.612 ns ( 84.81 % ) " "Info: Total cell delay = 2.612 ns ( 84.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.468 ns ( 15.19 % ) " "Info: Total interconnect delay = 0.468 ns ( 15.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.080 ns" { clk clk_out } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.080 ns" { clk clk_out } { 0.000ns 0.468ns } { 0.000ns 2.612ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.685 ns" { clk_in clk_in~clkctrl clk } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.685 ns" { clk_in clk_in~combout clk_in~clkctrl clk } { 0.000ns 0.000ns 0.118ns 1.031ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.080 ns" { clk clk_out } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.080 ns" { clk clk_out } { 0.000ns 0.468ns } { 0.000ns 2.612ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}