fenpin1hz.tan.rpt

多功能电子钟

; N/A                                     ; 330.25 MHz ( period = 3.028 ns )                    ; tout[10] ; tout[24] ; clk_in     ; clk_in   ; None                        ; None                      ; 2.817 ns                ;
; N/A                                     ; 331.13 MHz ( period = 3.020 ns )                    ; tout[3]  ; tout[23] ; clk_in     ; clk_in   ; None                        ; None                      ; 2.809 ns                ;
; N/A                                     ; 332.56 MHz ( period = 3.007 ns )                    ; tout[7]  ; tout[11] ; clk_in     ; clk_in   ; None                        ; None                      ; 2.796 ns                ;
; N/A                                     ; 332.78 MHz ( period = 3.005 ns )                    ; tout[7]  ; tout[14] ; clk_in     ; clk_in   ; None                        ; None                      ; 2.794 ns                ;
; N/A                                     ; 332.78 MHz ( period = 3.005 ns )                    ; tout[7]  ; tout[12] ; clk_in     ; clk_in   ; None                        ; None                      ; 2.794 ns                ;
; N/A                                     ; 332.89 MHz ( period = 3.004 ns )                    ; tout[7]  ; clk      ; clk_in     ; clk_in   ; None                        ; None                      ; 2.793 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;          ;          ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------+
; tco                                                             ;
+-------+--------------+------------+------+---------+------------+
; Slack ; Required tco ; Actual tco ; From ; To      ; From Clock ;
+-------+--------------+------------+------+---------+------------+
; N/A   ; None         ; 6.015 ns   ; clk  ; clk_out ; clk_in     ;
+-------+--------------+------------+------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Mar 24 20:07:55 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fenpin1Hz -c fenpin1Hz --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk_in" is an undefined clock
Info: Clock "clk_in" has Internal fmax of 253.49 MHz between source register "tout[0]" and destination register "tout[21]" (period= 3.945 ns)
    Info: + Longest register to register delay is 3.734 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X63_Y22_N9; Fanout = 3; REG Node = 'tout[0]'
        Info: 2: + IC(0.318 ns) + CELL(0.393 ns) = 0.711 ns; Loc. = LCCOMB_X63_Y22_N8; Fanout = 2; COMB Node = 'Add0~301'
        Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.782 ns; Loc. = LCCOMB_X63_Y22_N10; Fanout = 2; COMB Node = 'Add0~303'
        Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 0.853 ns; Loc. = LCCOMB_X63_Y22_N12; Fanout = 2; COMB Node = 'Add0~305'
        Info: 5: + IC(0.000 ns) + CELL(0.159 ns) = 1.012 ns; Loc. = LCCOMB_X63_Y22_N14; Fanout = 2; COMB Node = 'Add0~307'
        Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.083 ns; Loc. = LCCOMB_X63_Y22_N16; Fanout = 2; COMB Node = 'Add0~309'
        Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.154 ns; Loc. = LCCOMB_X63_Y22_N18; Fanout = 2; COMB Node = 'Add0~311'
        Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.225 ns; Loc. = LCCOMB_X63_Y22_N20; Fanout = 2; COMB Node = 'Add0~313'
        Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 1.296 ns; Loc. = LCCOMB_X63_Y22_N22; Fanout = 2; COMB Node = 'Add0~315'
        Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 1.367 ns; Loc. = LCCOMB_X63_Y22_N24; Fanout = 2; COMB Node = 'Add0~317'
        Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 1.438 ns; Loc. = LCCOMB_X63_Y22_N26; Fanout = 2; COMB Node = 'Add0~319'
        Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 1.509 ns; Loc. = LCCOMB_X63_Y22_N28; Fanout = 2; COMB Node = 'Add0~321'
        Info: 13: + IC(0.000 ns) + CELL(0.146 ns) = 1.655 ns; Loc. = LCCOMB_X63_Y22_N30; Fanout = 2; COMB Node = 'Add0~323'
        Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 1.726 ns; Loc. = LCCOMB_X63_Y21_N0; Fanout = 2; COMB Node = 'Add0~325'
        Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 1.797 ns; Loc. = LCCOMB_X63_Y21_N2; Fanout = 2; COMB Node = 'Add0~327'
        Info: 16: + IC(0.000 ns) + CELL(0.071 ns) = 1.868 ns; Loc. = LCCOMB_X63_Y21_N4; Fanout = 2; COMB Node = 'Add0~329'
        Info: 17: + IC(0.000 ns) + CELL(0.071 ns) = 1.939 ns; Loc. = LCCOMB_X63_Y21_N6; Fanout = 2; COMB Node = 'Add0~331'
        Info: 18: + IC(0.000 ns) + CELL(0.071 ns) = 2.010 ns; Loc. = LCCOMB_X63_Y21_N8; Fanout = 2; COMB Node = 'Add0~333'
        Info: 19: + IC(0.000 ns) + CELL(0.071 ns) = 2.081 ns; Loc. = LCCOMB_X63_Y21_N10; Fanout = 2; COMB Node = 'Add0~335'
        Info: 20: + IC(0.000 ns) + CELL(0.071 ns) = 2.152 ns; Loc. = LCCOMB_X63_Y21_N12; Fanout = 2; COMB Node = 'Add0~337'
        Info: 21: + IC(0.000 ns) + CELL(0.159 ns) = 2.311 ns; Loc. = LCCOMB_X63_Y21_N14; Fanout = 2; COMB Node = 'Add0~339'
        Info: 22: + IC(0.000 ns) + CELL(0.071 ns) = 2.382 ns; Loc. = LCCOMB_X63_Y21_N16; Fanout = 2; COMB Node = 'Add0~341'
        Info: 23: + IC(0.000 ns) + CELL(0.410 ns) = 2.792 ns; Loc. = LCCOMB_X63_Y21_N18; Fanout = 1; COMB Node = 'Add0~342'
        Info: 24: + IC(0.438 ns) + CELL(0.420 ns) = 3.650 ns; Loc. = LCCOMB_X64_Y21_N12; Fanout = 1; COMB Node = 'tout~233'
        Info: 25: + IC(0.000 ns) + CELL(0.084 ns) = 3.734 ns; Loc. = LCFF_X64_Y21_N13; Fanout = 3; REG Node = 'tout[21]'
        Info: Total cell delay = 2.978 ns ( 79.75 % )
        Info: Total interconnect delay = 0.756 ns ( 20.25 % )
    Info: - Smallest clock skew is 0.003 ns
        Info: + Shortest clock path from clock "clk_in" to destination register is 2.685 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk_in'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 26; COMB Node = 'clk_in~clkctrl'
            Info: 3: + IC(1.031 ns) + CELL(0.537 ns) = 2.685 ns; Loc. = LCFF_X64_Y21_N13; Fanout = 3; REG Node = 'tout[21]'
            Info: Total cell delay = 1.536 ns ( 57.21 % )
            Info: Total interconnect delay = 1.149 ns ( 42.79 % )
        Info: - Longest clock path from clock "clk_in" to source register is 2.682 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk_in'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 26; COMB Node = 'clk_in~clkctrl'
            Info: 3: + IC(1.028 ns) + CELL(0.537 ns) = 2.682 ns; Loc. = LCFF_X63_Y22_N9; Fanout = 3; REG Node = 'tout[0]'
            Info: Total cell delay = 1.536 ns ( 57.27 % )
            Info: Total interconnect delay = 1.146 ns ( 42.73 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tco from clock "clk_in" to destination pin "clk_out" through register "clk" is 6.015 ns
    Info: + Longest clock path from clock "clk_in" to source register is 2.685 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk_in'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 26; COMB Node = 'clk_in~clkctrl'
        Info: 3: + IC(1.031 ns) + CELL(0.537 ns) = 2.685 ns; Loc. = LCFF_X64_Y21_N15; Fanout = 2; REG Node = 'clk'
        Info: Total cell delay = 1.536 ns ( 57.21 % )
        Info: Total interconnect delay = 1.149 ns ( 42.79 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.080 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X64_Y21_N15; Fanout = 2; REG Node = 'clk'
        Info: 2: + IC(0.468 ns) + CELL(2.612 ns) = 3.080 ns; Loc. = PIN_M21; Fanout = 0; PIN Node = 'clk_out'
        Info: Total cell delay = 2.612 ns ( 84.81 % )
        Info: Total interconnect delay = 0.468 ns ( 15.19 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Mar 24 20:07:56 2009
    Info: Elapsed time: 00:00:02