fenpin1khz.tan.qmsg

多功能电子钟

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_in register tout\[0\] register tout\[13\] 326.05 MHz 3.067 ns Internal " "Info: Clock \"clk_in\" has Internal fmax of 326.05 MHz between source register \"tout\[0\]\" and destination register \"tout\[13\]\" (period= 3.067 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.852 ns + Longest register register " "Info: + Longest register to register delay is 2.852 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tout\[0\] 1 REG LCFF_X42_Y12_N1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X42_Y12_N1; Fanout = 3; REG Node = 'tout\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { tout[0] } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.313 ns) + CELL(0.393 ns) 0.706 ns Add0~181 2 COMB LCCOMB_X42_Y12_N0 2 " "Info: 2: + IC(0.313 ns) + CELL(0.393 ns) = 0.706 ns; Loc. = LCCOMB_X42_Y12_N0; Fanout = 2; COMB Node = 'Add0~181'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.706 ns" { tout[0] Add0~181 } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.777 ns Add0~183 3 COMB LCCOMB_X42_Y12_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.777 ns; Loc. = LCCOMB_X42_Y12_N2; Fanout = 2; COMB Node = 'Add0~183'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~181 Add0~183 } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.848 ns Add0~185 4 COMB LCCOMB_X42_Y12_N4 2 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 0.848 ns; Loc. = LCCOMB_X42_Y12_N4; Fanout = 2; COMB Node = 'Add0~185'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~183 Add0~185 } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.919 ns Add0~187 5 COMB LCCOMB_X42_Y12_N6 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 0.919 ns; Loc. = LCCOMB_X42_Y12_N6; Fanout = 2; COMB Node = 'Add0~187'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~185 Add0~187 } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.990 ns Add0~189 6 COMB LCCOMB_X42_Y12_N8 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 0.990 ns; Loc. = LCCOMB_X42_Y12_N8; Fanout = 2; COMB Node = 'Add0~189'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~187 Add0~189 } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.061 ns Add0~191 7 COMB LCCOMB_X42_Y12_N10 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.061 ns; Loc. = LCCOMB_X42_Y12_N10; Fanout = 2; COMB Node = 'Add0~191'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~189 Add0~191 } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.132 ns Add0~193 8 COMB LCCOMB_X42_Y12_N12 2 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.132 ns; Loc. = LCCOMB_X42_Y12_N12; Fanout = 2; COMB Node = 'Add0~193'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~191 Add0~193 } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 1.291 ns Add0~195 9 COMB LCCOMB_X42_Y12_N14 2 " "Info: 9: + IC(0.000 ns) + CELL(0.159 ns) = 1.291 ns; Loc. = LCCOMB_X42_Y12_N14; Fanout = 2; COMB Node = 'Add0~195'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.159 ns" { Add0~193 Add0~195 } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.362 ns Add0~197 10 COMB LCCOMB_X42_Y12_N16 2 " "Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 1.362 ns; Loc. = LCCOMB_X42_Y12_N16; Fanout = 2; COMB Node = 'Add0~197'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~195 Add0~197 } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.433 ns Add0~199 11 COMB LCCOMB_X42_Y12_N18 2 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 1.433 ns; Loc. = LCCOMB_X42_Y12_N18; Fanout = 2; COMB Node = 'Add0~199'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~197 Add0~199 } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.504 ns Add0~201 12 COMB LCCOMB_X42_Y12_N20 2 " "Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 1.504 ns; Loc. = LCCOMB_X42_Y12_N20; Fanout = 2; COMB Node = 'Add0~201'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~199 Add0~201 } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.575 ns Add0~203 13 COMB LCCOMB_X42_Y12_N22 2 " "Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 1.575 ns; Loc. = LCCOMB_X42_Y12_N22; Fanout = 2; COMB Node = 'Add0~203'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~201 Add0~203 } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.646 ns Add0~205 14 COMB LCCOMB_X42_Y12_N24 2 " "Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 1.646 ns; Loc. = LCCOMB_X42_Y12_N24; Fanout = 2; COMB Node = 'Add0~205'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~203 Add0~205 } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 2.056 ns Add0~206 15 COMB LCCOMB_X42_Y12_N26 1 " "Info: 15: + IC(0.000 ns) + CELL(0.410 ns) = 2.056 ns; Loc. = LCCOMB_X42_Y12_N26; Fanout = 1; COMB Node = 'Add0~206'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { Add0~205 Add0~206 } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.275 ns) 2.768 ns tout~369 16 COMB LCCOMB_X41_Y12_N30 1 " "Info: 16: + IC(0.437 ns) + CELL(0.275 ns) = 2.768 ns; Loc. = LCCOMB_X41_Y12_N30; Fanout = 1; COMB Node = 'tout~369'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.712 ns" { Add0~206 tout~369 } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.852 ns tout\[13\] 17 REG LCFF_X41_Y12_N31 3 " "Info: 17: + IC(0.000 ns) + CELL(0.084 ns) = 2.852 ns; Loc. = LCFF_X41_Y12_N31; Fanout = 3; REG Node = 'tout\[13\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { tout~369 tout[13] } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.102 ns ( 73.70 % ) " "Info: Total cell delay = 2.102 ns ( 73.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.750 ns ( 26.30 % ) " "Info: Total interconnect delay = 0.750 ns ( 26.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.852 ns" { tout[0] Add0~181 Add0~183 Add0~185 Add0~187 Add0~189 Add0~191 Add0~193 Add0~195 Add0~197 Add0~199 Add0~201 Add0~203 Add0~205 Add0~206 tout~369 tout[13] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.852 ns" { tout[0] Add0~181 Add0~183 Add0~185 Add0~187 Add0~189 Add0~191 Add0~193 Add0~195 Add0~197 Add0~199 Add0~201 Add0~203 Add0~205 Add0~206 tout~369 tout[13] } { 0.000ns 0.313ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.437ns 0.000ns } { 0.000ns 0.393ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.275ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.001 ns - Smallest " "Info: - Smallest clock skew is -0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 2.659 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_in\" to destination register is 2.659 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk_in 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk_in'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk_in~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk_in~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk_in clk_in~clkctrl } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.005 ns) + CELL(0.537 ns) 2.659 ns tout\[13\] 3 REG LCFF_X41_Y12_N31 3 " "Info: 3: + IC(1.005 ns) + CELL(0.537 ns) = 2.659 ns; Loc. = LCFF_X41_Y12_N31; Fanout = 3; REG Node = 'tout\[13\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.542 ns" { clk_in~clkctrl tout[13] } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.77 % ) " "Info: Total cell delay = 1.536 ns ( 57.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.123 ns ( 42.23 % ) " "Info: Total interconnect delay = 1.123 ns ( 42.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.659 ns" { clk_in clk_in~clkctrl tout[13] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.659 ns" { clk_in clk_in~combout clk_in~clkctrl tout[13] } { 0.000ns 0.000ns 0.118ns 1.005ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 2.660 ns - Longest register " "Info: - Longest clock path from clock \"clk_in\" to source register is 2.660 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk_in 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk_in'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk_in~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk_in~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk_in clk_in~clkctrl } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.006 ns) + CELL(0.537 ns) 2.660 ns tout\[0\] 3 REG LCFF_X42_Y12_N1 3 " "Info: 3: + IC(1.006 ns) + CELL(0.537 ns) = 2.660 ns; Loc. = LCFF_X42_Y12_N1; Fanout = 3; REG Node = 'tout\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.543 ns" { clk_in~clkctrl tout[0] } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.74 % ) " "Info: Total cell delay = 1.536 ns ( 57.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.124 ns ( 42.26 % ) " "Info: Total interconnect delay = 1.124 ns ( 42.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.660 ns" { clk_in clk_in~clkctrl tout[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.660 ns" { clk_in clk_in~combout clk_in~clkctrl tout[0] } { 0.000ns 0.000ns 0.118ns 1.006ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.659 ns" { clk_in clk_in~clkctrl tout[13] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.659 ns" { clk_in clk_in~combout clk_in~clkctrl tout[13] } { 0.000ns 0.000ns 0.118ns 1.005ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.660 ns" { clk_in clk_in~clkctrl tout[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.660 ns" { clk_in clk_in~combout clk_in~clkctrl tout[0] } { 0.000ns 0.000ns 0.118ns 1.006ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.852 ns" { tout[0] Add0~181 Add0~183 Add0~185 Add0~187 Add0~189 Add0~191 Add0~193 Add0~195 Add0~197 Add0~199 Add0~201 Add0~203 Add0~205 Add0~206 tout~369 tout[13] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.852 ns" { tout[0] Add0~181 Add0~183 Add0~185 Add0~187 Add0~189 Add0~191 Add0~193 Add0~195 Add0~197 Add0~199 Add0~201 Add0~203 Add0~205 Add0~206 tout~369 tout[13] } { 0.000ns 0.313ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.437ns 0.000ns } { 0.000ns 0.393ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.275ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.659 ns" { clk_in clk_in~clkctrl tout[13] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.659 ns" { clk_in clk_in~combout clk_in~clkctrl tout[13] } { 0.000ns 0.000ns 0.118ns 1.005ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.660 ns" { clk_in clk_in~clkctrl tout[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.660 ns" { clk_in clk_in~combout clk_in~clkctrl tout[0] } { 0.000ns 0.000ns 0.118ns 1.006ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_in clk_out clk 7.013 ns register " "Info: tco from clock \"clk_in\" to destination pin \"clk_out\" through register \"clk\" is 7.013 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 2.659 ns + Longest register " "Info: + Longest clock path from clock \"clk_in\" to source register is 2.659 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk_in 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk_in'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk_in~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk_in~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk_in clk_in~clkctrl } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.005 ns) + CELL(0.537 ns) 2.659 ns clk 3 REG LCFF_X41_Y12_N1 2 " "Info: 3: + IC(1.005 ns) + CELL(0.537 ns) = 2.659 ns; Loc. = LCFF_X41_Y12_N1; Fanout = 2; REG Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.542 ns" { clk_in~clkctrl clk } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.77 % ) " "Info: Total cell delay = 1.536 ns ( 57.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.123 ns ( 42.23 % ) " "Info: Total interconnect delay = 1.123 ns ( 42.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.659 ns" { clk_in clk_in~clkctrl clk } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.659 ns" { clk_in clk_in~combout clk_in~clkctrl clk } { 0.000ns 0.000ns 0.118ns 1.005ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.104 ns + Longest register pin " "Info: + Longest register to pin delay is 4.104 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk 1 REG LCFF_X41_Y12_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X41_Y12_N1; Fanout = 2; REG Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.336 ns) + CELL(2.768 ns) 4.104 ns clk_out 2 PIN PIN_AC15 0 " "Info: 2: + IC(1.336 ns) + CELL(2.768 ns) = 4.104 ns; Loc. = PIN_AC15; Fanout = 0; PIN Node = 'clk_out'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.104 ns" { clk clk_out } "NODE_NAME" } } { "fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.768 ns ( 67.45 % ) " "Info: Total cell delay = 2.768 ns ( 67.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.336 ns ( 32.55 % ) " "Info: Total interconnect delay = 1.336 ns ( 32.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.104 ns" { clk clk_out } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.104 ns" { clk clk_out } { 0.000ns 1.336ns } { 0.000ns 2.768ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.659 ns" { clk_in clk_in~clkctrl clk } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.659 ns" { clk_in clk_in~combout clk_in~clkctrl clk } { 0.000ns 0.000ns 0.118ns 1.005ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.104 ns" { clk clk_out } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.104 ns" { clk clk_out } { 0.000ns 1.336ns } { 0.000ns 2.768ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 24 20:11:36 2009 " "Info: Processing ended: Tue Mar 24 20:11:36 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}