fenpin1khz.tan.rpt

多功能电子钟

; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[7]  ; tout[3]  ; clk_in     ; clk_in   ; None                        ; None                      ; 1.412 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[12] ; tout[3]  ; clk_in     ; clk_in   ; None                        ; None                      ; 1.405 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[14] ; tout[14] ; clk_in     ; clk_in   ; None                        ; None                      ; 1.398 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[3]  ; tout[4]  ; clk_in     ; clk_in   ; None                        ; None                      ; 1.386 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[8]  ; tout[9]  ; clk_in     ; clk_in   ; None                        ; None                      ; 1.385 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[5]  ; tout[6]  ; clk_in     ; clk_in   ; None                        ; None                      ; 1.384 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[9]  ; tout[12] ; clk_in     ; clk_in   ; None                        ; None                      ; 1.347 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[1]  ; tout[4]  ; clk_in     ; clk_in   ; None                        ; None                      ; 1.346 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[10] ; tout[12] ; clk_in     ; clk_in   ; None                        ; None                      ; 1.308 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[0]  ; clk      ; clk_in     ; clk_in   ; None                        ; None                      ; 1.291 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[9]  ; tout[11] ; clk_in     ; clk_in   ; None                        ; None                      ; 1.276 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[4]  ; tout[6]  ; clk_in     ; clk_in   ; None                        ; None                      ; 1.272 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[2]  ; tout[4]  ; clk_in     ; clk_in   ; None                        ; None                      ; 1.271 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[0]  ; tout[2]  ; clk_in     ; clk_in   ; None                        ; None                      ; 1.271 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[5]  ; clk      ; clk_in     ; clk_in   ; None                        ; None                      ; 1.255 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[10] ; tout[11] ; clk_in     ; clk_in   ; None                        ; None                      ; 1.237 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[11] ; tout[12] ; clk_in     ; clk_in   ; None                        ; None                      ; 1.205 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[9]  ; tout[10] ; clk_in     ; clk_in   ; None                        ; None                      ; 1.205 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[1]  ; tout[2]  ; clk_in     ; clk_in   ; None                        ; None                      ; 1.204 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[0]  ; tout[1]  ; clk_in     ; clk_in   ; None                        ; None                      ; 1.200 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[3]  ; clk      ; clk_in     ; clk_in   ; None                        ; None                      ; 1.197 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[2]  ; clk      ; clk_in     ; clk_in   ; None                        ; None                      ; 1.158 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[14] ; tout[3]  ; clk_in     ; clk_in   ; None                        ; None                      ; 1.128 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[5]  ; tout[3]  ; clk_in     ; clk_in   ; None                        ; None                      ; 1.116 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[12] ; tout[12] ; clk_in     ; clk_in   ; None                        ; None                      ; 0.851 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[10] ; tout[10] ; clk_in     ; clk_in   ; None                        ; None                      ; 0.851 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[6]  ; tout[6]  ; clk_in     ; clk_in   ; None                        ; None                      ; 0.844 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[9]  ; tout[9]  ; clk_in     ; clk_in   ; None                        ; None                      ; 0.822 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[11] ; tout[11] ; clk_in     ; clk_in   ; None                        ; None                      ; 0.822 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[1]  ; tout[1]  ; clk_in     ; clk_in   ; None                        ; None                      ; 0.821 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[4]  ; tout[4]  ; clk_in     ; clk_in   ; None                        ; None                      ; 0.818 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[0]  ; tout[0]  ; clk_in     ; clk_in   ; None                        ; None                      ; 0.817 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; tout[2]  ; tout[2]  ; clk_in     ; clk_in   ; None                        ; None                      ; 0.817 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; clk      ; clk      ; clk_in     ; clk_in   ; None                        ; None                      ; 0.407 ns                ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------+
; tco                                                             ;
+-------+--------------+------------+------+---------+------------+
; Slack ; Required tco ; Actual tco ; From ; To      ; From Clock ;
+-------+--------------+------------+------+---------+------------+
; N/A   ; None         ; 7.013 ns   ; clk  ; clk_out ; clk_in     ;
+-------+--------------+------------+------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Mar 24 20:11:35 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fenpin1kHz -c fenpin1kHz --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk_in" is an undefined clock
Info: Clock "clk_in" has Internal fmax of 326.05 MHz between source register "tout[0]" and destination register "tout[13]" (period= 3.067 ns)
    Info: + Longest register to register delay is 2.852 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X42_Y12_N1; Fanout = 3; REG Node = 'tout[0]'
        Info: 2: + IC(0.313 ns) + CELL(0.393 ns) = 0.706 ns; Loc. = LCCOMB_X42_Y12_N0; Fanout = 2; COMB Node = 'Add0~181'
        Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.777 ns; Loc. = LCCOMB_X42_Y12_N2; Fanout = 2; COMB Node = 'Add0~183'
        Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 0.848 ns; Loc. = LCCOMB_X42_Y12_N4; Fanout = 2; COMB Node = 'Add0~185'
        Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 0.919 ns; Loc. = LCCOMB_X42_Y12_N6; Fanout = 2; COMB Node = 'Add0~187'
        Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 0.990 ns; Loc. = LCCOMB_X42_Y12_N8; Fanout = 2; COMB Node = 'Add0~189'
        Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.061 ns; Loc. = LCCOMB_X42_Y12_N10; Fanout = 2; COMB Node = 'Add0~191'
        Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.132 ns; Loc. = LCCOMB_X42_Y12_N12; Fanout = 2; COMB Node = 'Add0~193'
        Info: 9: + IC(0.000 ns) + CELL(0.159 ns) = 1.291 ns; Loc. = LCCOMB_X42_Y12_N14; Fanout = 2; COMB Node = 'Add0~195'
        Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 1.362 ns; Loc. = LCCOMB_X42_Y12_N16; Fanout = 2; COMB Node = 'Add0~197'
        Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 1.433 ns; Loc. = LCCOMB_X42_Y12_N18; Fanout = 2; COMB Node = 'Add0~199'
        Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 1.504 ns; Loc. = LCCOMB_X42_Y12_N20; Fanout = 2; COMB Node = 'Add0~201'
        Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 1.575 ns; Loc. = LCCOMB_X42_Y12_N22; Fanout = 2; COMB Node = 'Add0~203'
        Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 1.646 ns; Loc. = LCCOMB_X42_Y12_N24; Fanout = 2; COMB Node = 'Add0~205'
        Info: 15: + IC(0.000 ns) + CELL(0.410 ns) = 2.056 ns; Loc. = LCCOMB_X42_Y12_N26; Fanout = 1; COMB Node = 'Add0~206'
        Info: 16: + IC(0.437 ns) + CELL(0.275 ns) = 2.768 ns; Loc. = LCCOMB_X41_Y12_N30; Fanout = 1; COMB Node = 'tout~369'
        Info: 17: + IC(0.000 ns) + CELL(0.084 ns) = 2.852 ns; Loc. = LCFF_X41_Y12_N31; Fanout = 3; REG Node = 'tout[13]'
        Info: Total cell delay = 2.102 ns ( 73.70 % )
        Info: Total interconnect delay = 0.750 ns ( 26.30 % )
    Info: - Smallest clock skew is -0.001 ns
        Info: + Shortest clock path from clock "clk_in" to destination register is 2.659 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk_in'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk_in~clkctrl'
            Info: 3: + IC(1.005 ns) + CELL(0.537 ns) = 2.659 ns; Loc. = LCFF_X41_Y12_N31; Fanout = 3; REG Node = 'tout[13]'
            Info: Total cell delay = 1.536 ns ( 57.77 % )
            Info: Total interconnect delay = 1.123 ns ( 42.23 % )
        Info: - Longest clock path from clock "clk_in" to source register is 2.660 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk_in'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk_in~clkctrl'
            Info: 3: + IC(1.006 ns) + CELL(0.537 ns) = 2.660 ns; Loc. = LCFF_X42_Y12_N1; Fanout = 3; REG Node = 'tout[0]'
            Info: Total cell delay = 1.536 ns ( 57.74 % )
            Info: Total interconnect delay = 1.124 ns ( 42.26 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tco from clock "clk_in" to destination pin "clk_out" through register "clk" is 7.013 ns
    Info: + Longest clock path from clock "clk_in" to source register is 2.659 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk_in'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk_in~clkctrl'
        Info: 3: + IC(1.005 ns) + CELL(0.537 ns) = 2.659 ns; Loc. = LCFF_X41_Y12_N1; Fanout = 2; REG Node = 'clk'
        Info: Total cell delay = 1.536 ns ( 57.77 % )
        Info: Total interconnect delay = 1.123 ns ( 42.23 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 4.104 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X41_Y12_N1; Fanout = 2; REG Node = 'clk'
        Info: 2: + IC(1.336 ns) + CELL(2.768 ns) = 4.104 ns; Loc. = PIN_AC15; Fanout = 0; PIN Node = 'clk_out'
        Info: Total cell delay = 2.768 ns ( 67.45 % )
        Info: Total interconnect delay = 1.336 ns ( 32.55 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Mar 24 20:11:36 2009
    Info: Elapsed time: 00:00:02