fenpin1khz.tan.rpt

多功能电子钟

Timing Analyzer report for fenpin1kHz
Tue Mar 24 20:11:36 2009
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk_in'
  6. tco
  7. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                             ;
+------------------------------+-------+---------------+----------------------------------+---------+----------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From    ; To       ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+---------+----------+------------+----------+--------------+
; Worst-case tco               ; N/A   ; None          ; 7.013 ns                         ; clk     ; clk_out  ; clk_in     ; --       ; 0            ;
; Clock Setup: 'clk_in'        ; N/A   ; None          ; 326.05 MHz ( period = 3.067 ns ) ; tout[0] ; tout[13] ; clk_in     ; clk_in   ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;         ;          ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+---------+----------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk_in          ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk_in'                                                                                                                                                                    ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From     ; To       ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 326.05 MHz ( period = 3.067 ns )               ; tout[0]  ; tout[13] ; clk_in     ; clk_in   ; None                        ; None                      ; 2.852 ns                ;
; N/A   ; 329.06 MHz ( period = 3.039 ns )               ; tout[3]  ; tout[13] ; clk_in     ; clk_in   ; None                        ; None                      ; 2.825 ns                ;
; N/A   ; 333.33 MHz ( period = 3.000 ns )               ; tout[1]  ; tout[13] ; clk_in     ; clk_in   ; None                        ; None                      ; 2.785 ns                ;
; N/A   ; 341.88 MHz ( period = 2.925 ns )               ; tout[2]  ; tout[13] ; clk_in     ; clk_in   ; None                        ; None                      ; 2.710 ns                ;
; N/A   ; 345.42 MHz ( period = 2.895 ns )               ; tout[5]  ; tout[13] ; clk_in     ; clk_in   ; None                        ; None                      ; 2.681 ns                ;
; N/A   ; 354.86 MHz ( period = 2.818 ns )               ; tout[0]  ; tout[14] ; clk_in     ; clk_in   ; None                        ; None                      ; 2.604 ns                ;
; N/A   ; 358.29 MHz ( period = 2.791 ns )               ; tout[7]  ; tout[13] ; clk_in     ; clk_in   ; None                        ; None                      ; 2.577 ns                ;
; N/A   ; 358.42 MHz ( period = 2.790 ns )               ; tout[3]  ; tout[14] ; clk_in     ; clk_in   ; None                        ; None                      ; 2.577 ns                ;
; N/A   ; 359.20 MHz ( period = 2.784 ns )               ; tout[4]  ; tout[13] ; clk_in     ; clk_in   ; None                        ; None                      ; 2.569 ns                ;
; N/A   ; 363.50 MHz ( period = 2.751 ns )               ; tout[1]  ; tout[14] ; clk_in     ; clk_in   ; None                        ; None                      ; 2.537 ns                ;
; N/A   ; 368.73 MHz ( period = 2.712 ns )               ; tout[0]  ; tout[8]  ; clk_in     ; clk_in   ; None                        ; None                      ; 2.497 ns                ;
; N/A   ; 372.58 MHz ( period = 2.684 ns )               ; tout[3]  ; tout[8]  ; clk_in     ; clk_in   ; None                        ; None                      ; 2.470 ns                ;
; N/A   ; 373.69 MHz ( period = 2.676 ns )               ; tout[2]  ; tout[14] ; clk_in     ; clk_in   ; None                        ; None                      ; 2.462 ns                ;
; N/A   ; 374.39 MHz ( period = 2.671 ns )               ; tout[6]  ; tout[13] ; clk_in     ; clk_in   ; None                        ; None                      ; 2.456 ns                ;
; N/A   ; 377.93 MHz ( period = 2.646 ns )               ; tout[5]  ; tout[14] ; clk_in     ; clk_in   ; None                        ; None                      ; 2.433 ns                ;
; N/A   ; 378.07 MHz ( period = 2.645 ns )               ; tout[1]  ; tout[8]  ; clk_in     ; clk_in   ; None                        ; None                      ; 2.430 ns                ;
; N/A   ; 385.06 MHz ( period = 2.597 ns )               ; tout[11] ; tout[8]  ; clk_in     ; clk_in   ; None                        ; None                      ; 2.382 ns                ;
; N/A   ; 385.36 MHz ( period = 2.595 ns )               ; tout[8]  ; tout[13] ; clk_in     ; clk_in   ; None                        ; None                      ; 2.381 ns                ;
; N/A   ; 385.36 MHz ( period = 2.595 ns )               ; tout[11] ; tout[5]  ; clk_in     ; clk_in   ; None                        ; None                      ; 2.380 ns                ;
; N/A   ; 385.51 MHz ( period = 2.594 ns )               ; tout[11] ; tout[13] ; clk_in     ; clk_in   ; None                        ; None                      ; 2.379 ns                ;
; N/A   ; 385.80 MHz ( period = 2.592 ns )               ; tout[11] ; tout[7]  ; clk_in     ; clk_in   ; None                        ; None                      ; 2.377 ns                ;
; N/A   ; 386.40 MHz ( period = 2.588 ns )               ; tout[11] ; clk      ; clk_in     ; clk_in   ; None                        ; None                      ; 2.373 ns                ;
; N/A   ; 389.11 MHz ( period = 2.570 ns )               ; tout[2]  ; tout[8]  ; clk_in     ; clk_in   ; None                        ; None                      ; 2.355 ns                ;
; N/A   ; 391.08 MHz ( period = 2.557 ns )               ; tout[11] ; tout[14] ; clk_in     ; clk_in   ; None                        ; None                      ; 2.343 ns                ;