📄 display1.tan.rpt
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Timing Analyzer report for display1
Tue Mar 24 20:33:43 2009
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------------+-------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------------+-------------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 9.626 ns ; BCDcode[3] ; display1[6] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------------+-------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C35F672C6 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------------+-------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------------+-------------+
; N/A ; None ; 9.626 ns ; BCDcode[3] ; display1[6] ;
; N/A ; None ; 9.591 ns ; BCDcode[3] ; display1[5] ;
; N/A ; None ; 9.505 ns ; BCDcode[3] ; display1[0] ;
; N/A ; None ; 9.457 ns ; BCDcode[3] ; display1[1] ;
; N/A ; None ; 9.337 ns ; BCDcode[3] ; display1[4] ;
; N/A ; None ; 9.330 ns ; BCDcode[3] ; display1[2] ;
; N/A ; None ; 9.322 ns ; BCDcode[4] ; display2[6] ;
; N/A ; None ; 9.320 ns ; BCDcode[4] ; display2[2] ;
; N/A ; None ; 9.316 ns ; BCDcode[4] ; display2[3] ;
; N/A ; None ; 9.307 ns ; BCDcode[3] ; display1[3] ;
; N/A ; None ; 9.285 ns ; BCDcode[4] ; display2[1] ;
; N/A ; None ; 9.249 ns ; BCDcode[6] ; display2[6] ;
; N/A ; None ; 9.244 ns ; BCDcode[6] ; display2[3] ;
; N/A ; None ; 9.212 ns ; BCDcode[2] ; display1[6] ;
; N/A ; None ; 9.207 ns ; BCDcode[7] ; display2[6] ;
; N/A ; None ; 9.207 ns ; BCDcode[6] ; display2[2] ;
; N/A ; None ; 9.206 ns ; BCDcode[5] ; display2[6] ;
; N/A ; None ; 9.203 ns ; BCDcode[7] ; display2[3] ;
; N/A ; None ; 9.202 ns ; BCDcode[7] ; display2[2] ;
; N/A ; None ; 9.201 ns ; BCDcode[6] ; display2[1] ;
; N/A ; None ; 9.200 ns ; BCDcode[5] ; display2[3] ;
; N/A ; None ; 9.197 ns ; BCDcode[5] ; display2[2] ;
; N/A ; None ; 9.172 ns ; BCDcode[2] ; display1[5] ;
; N/A ; None ; 9.166 ns ; BCDcode[5] ; display2[1] ;
; N/A ; None ; 9.165 ns ; BCDcode[4] ; display2[5] ;
; N/A ; None ; 9.165 ns ; BCDcode[7] ; display2[1] ;
; N/A ; None ; 9.093 ns ; BCDcode[6] ; display2[5] ;
; N/A ; None ; 9.086 ns ; BCDcode[2] ; display1[0] ;
; N/A ; None ; 9.052 ns ; BCDcode[7] ; display2[5] ;
; N/A ; None ; 9.050 ns ; BCDcode[5] ; display2[5] ;
; N/A ; None ; 9.048 ns ; BCDcode[2] ; display1[1] ;
; N/A ; None ; 9.010 ns ; BCDcode[4] ; display2[0] ;
; N/A ; None ; 8.977 ns ; BCDcode[4] ; display2[4] ;
; N/A ; None ; 8.931 ns ; BCDcode[6] ; display2[4] ;
; N/A ; None ; 8.927 ns ; BCDcode[6] ; display2[0] ;
; N/A ; None ; 8.923 ns ; BCDcode[2] ; display1[2] ;
; N/A ; None ; 8.918 ns ; BCDcode[2] ; display1[4] ;
; N/A ; None ; 8.890 ns ; BCDcode[7] ; display2[4] ;
; N/A ; None ; 8.889 ns ; BCDcode[7] ; display2[0] ;
; N/A ; None ; 8.889 ns ; BCDcode[2] ; display1[3] ;
; N/A ; None ; 8.887 ns ; BCDcode[5] ; display2[4] ;
; N/A ; None ; 8.864 ns ; BCDcode[5] ; display2[0] ;
; N/A ; None ; 6.516 ns ; BCDcode[0] ; display1[6] ;
; N/A ; None ; 6.467 ns ; BCDcode[0] ; display1[5] ;
; N/A ; None ; 6.401 ns ; BCDcode[1] ; display1[6] ;
; N/A ; None ; 6.381 ns ; BCDcode[0] ; display1[0] ;
; N/A ; None ; 6.356 ns ; BCDcode[1] ; display1[5] ;
; N/A ; None ; 6.347 ns ; BCDcode[0] ; display1[1] ;
; N/A ; None ; 6.267 ns ; BCDcode[1] ; display1[0] ;
; N/A ; None ; 6.233 ns ; BCDcode[1] ; display1[1] ;
; N/A ; None ; 6.223 ns ; BCDcode[0] ; display1[2] ;
; N/A ; None ; 6.188 ns ; BCDcode[0] ; display1[4] ;
; N/A ; None ; 6.185 ns ; BCDcode[0] ; display1[3] ;
; N/A ; None ; 6.108 ns ; BCDcode[1] ; display1[2] ;
; N/A ; None ; 6.103 ns ; BCDcode[1] ; display1[4] ;
; N/A ; None ; 6.070 ns ; BCDcode[1] ; display1[3] ;
+-------+-------------------+-----------------+------------+-------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Tue Mar 24 20:33:43 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off display1 -c display1 --timing_analysis_only
Info: Longest tpd from source pin "BCDcode[3]" to destination pin "display1[6]" is 9.626 ns
Info: 1: + IC(0.000 ns) + CELL(0.870 ns) = 0.870 ns; Loc. = PIN_A4; Fanout = 7; PIN Node = 'BCDcode[3]'
Info: 2: + IC(4.903 ns) + CELL(0.438 ns) = 6.211 ns; Loc. = LCCOMB_X1_Y33_N0; Fanout = 1; COMB Node = 'Mux0~3'
Info: 3: + IC(0.626 ns) + CELL(2.789 ns) = 9.626 ns; Loc. = PIN_E5; Fanout = 0; PIN Node = 'display1[6]'
Info: Total cell delay = 4.097 ns ( 42.56 % )
Info: Total interconnect delay = 5.529 ns ( 57.44 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Tue Mar 24 20:33:43 2009
Info: Elapsed time: 00:00:01
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