display1.vhd

来自「多功能电子钟」· VHDL 代码 · 共 42 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity display1 is
port( BCDcode : in std_logic_vector(7 downto 0);
      display1 : out std_logic_vector(6 downto 0);
      display2 : out std_logic_vector(6 downto 0));
end entity;

architecture behav of display1 is
begin
  process(BCDcode)
  begin
      case BCDcode(3 downto 0) is
        when "0000"=>display1<="1000000";
        when "0001"=>display1<="1111001";
        when "0010"=>display1<="0100100";
        when "0011"=>display1<="0110000";
        when "0100"=>display1<="0011001";
        when "0101"=>display1<="0010010";
        when "0110"=>display1<="0000010";
        when "0111"=>display1<="1111000";
        when "1000"=>display1<="0000000";
        when "1001"=>display1<="0011000";
        when others=>display1<="1111111";
      end case;
      case BCDcode(7 downto 4) is
        when "0000"=>display2<="1000000";
        when "0001"=>display2<="1111001";
        when "0010"=>display2<="0100100";
        when "0011"=>display2<="0110000";
        when "0100"=>display2<="0011001";
        when "0101"=>display2<="0010010";
        when "0110"=>display2<="0000010";
        when "0111"=>display2<="1111000";
        when "1000"=>display2<="0000000";
        when "1001"=>display2<="0011000";
        when others=>display2<="1111111";
      end case;
  end process;

end behav;