bb.tan.qmsg

多功能电子钟

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "20 " "Warning: Found 20 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "clock:inst\|clk_key1~26 " "Info: Detected gated clock \"clock:inst\|clk_key1~26\" as buffer" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 143 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clock:inst\|clk_key1~26" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "clock:inst\|clk_key2~26 " "Info: Detected gated clock \"clock:inst\|clk_key2~26\" as buffer" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 143 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clock:inst\|clk_key2~26" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "clock:inst\|clk_key3~23 " "Info: Detected gated clock \"clock:inst\|clk_key3~23\" as buffer" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 171 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clock:inst\|clk_key3~23" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "clock:inst\|clk_key4~22 " "Info: Detected gated clock \"clock:inst\|clk_key4~22\" as buffer" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 171 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clock:inst\|clk_key4~22" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clock:inst\|clk_100Hz " "Info: Detected ripple clock \"clock:inst\|clk_100Hz\" as buffer" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 17 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clock:inst\|clk_100Hz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "clock:inst\|clk_2 " "Info: Detected gated clock \"clock:inst\|clk_2\" as buffer" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 108 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clock:inst\|clk_2" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clock:inst\|temp3 " "Info: Detected ripple clock \"clock:inst\|temp3\" as buffer" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 19 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clock:inst\|temp3" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clock:inst\|temp2 " "Info: Detected ripple clock \"clock:inst\|temp2\" as buffer" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 19 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clock:inst\|temp2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin1Hz:inst5\|clk " "Info: Detected ripple clock \"fenpin1Hz:inst5\|clk\" as buffer" {  } { { "../fenpin1Hz/fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 14 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fenpin1Hz:inst5\|clk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "clock:inst\|adjust_key2 " "Info: Detected gated clock \"clock:inst\|adjust_key2\" as buffer" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 20 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clock:inst\|adjust_key2" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "clock:inst\|adjust_key1~6 " "Info: Detected gated clock \"clock:inst\|adjust_key1~6\" as buffer" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 20 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clock:inst\|adjust_key1~6" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "clock:inst\|clk_1~143 " "Info: Detected gated clock \"clock:inst\|clk_1~143\" as buffer" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 51 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clock:inst\|clk_1~143" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "clock:inst\|Equal3~92 " "Info: Detected gated clock \"clock:inst\|Equal3~92\" as buffer" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 230 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clock:inst\|Equal3~92" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "clock:inst\|Equal4~67 " "Info: Detected gated clock \"clock:inst\|Equal4~67\" as buffer" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 234 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clock:inst\|Equal4~67" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin1kHz:inst7\|clk " "Info: Detected ripple clock \"fenpin1kHz:inst7\|clk\" as buffer" {  } { { "../fenpin1kHz/fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 14 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fenpin1kHz:inst7\|clk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clock:inst\|temp1 " "Info: Detected ripple clock \"clock:inst\|temp1\" as buffer" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 19 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clock:inst\|temp1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clock:inst\|mode\[2\] " "Info: Detected ripple clock \"clock:inst\|mode\[2\]\" as buffer" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clock:inst\|mode\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clock:inst\|mode\[0\] " "Info: Detected ripple clock \"clock:inst\|mode\[0\]\" as buffer" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clock:inst\|mode\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "clock:inst\|funckey " "Info: Detected gated clock \"clock:inst\|funckey\" as buffer" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 20 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clock:inst\|funckey" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clock:inst\|mode\[1\] " "Info: Detected ripple clock \"clock:inst\|mode\[1\]\" as buffer" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clock:inst\|mode\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW\[2\] register clock:inst\|s1\[3\] register clock:inst\|h1\[3\] 210.93 MHz 4.741 ns Internal " "Info: Clock \"SW\[2\]\" has Internal fmax of 210.93 MHz between source register \"clock:inst\|s1\[3\]\" and destination register \"clock:inst\|h1\[3\]\" (period= 4.741 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.218 ns + Longest register register " "Info: + Longest register to register delay is 4.218 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clock:inst\|s1\[3\] 1 REG LCFF_X57_Y26_N25 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X57_Y26_N25; Fanout = 8; REG Node = 'clock:inst\|s1\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock:inst|s1[3] } "NODE_NAME" } } { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 103 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.734 ns) + CELL(0.275 ns) 1.009 ns clock:inst\|always2~202 2 COMB LCCOMB_X59_Y26_N28 8 " "Info: 2: + IC(0.734 ns) + CELL(0.275 ns) = 1.009 ns; Loc. = LCCOMB_X59_Y26_N28; Fanout = 8; COMB Node = 'clock:inst\|always2~202'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.009 ns" { clock:inst|s1[3] clock:inst|always2~202 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.263 ns) + CELL(0.150 ns) 1.422 ns clock:inst\|always2~203 3 COMB LCCOMB_X59_Y26_N12 13 " "Info: 3: + IC(0.263 ns) + CELL(0.150 ns) = 1.422 ns; Loc. = LCCOMB_X59_Y26_N12; Fanout = 13; COMB Node = 'clock:inst\|always2~203'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.413 ns" { clock:inst|always2~202 clock:inst|always2~203 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(0.150 ns) 1.831 ns clock:inst\|Add4~495 4 COMB LCCOMB_X59_Y26_N18 5 " "Info: 4: + IC(0.259 ns) + CELL(0.150 ns) = 1.831 ns; Loc. = LCCOMB_X59_Y26_N18; Fanout = 5; COMB Node = 'clock:inst\|Add4~495'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.409 ns" { clock:inst|always2~203 clock:inst|Add4~495 } "NODE_NAME" } } { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.262 ns) + CELL(0.149 ns) 2.242 ns clock:inst\|Add4~496 5 COMB LCCOMB_X59_Y26_N16 2 " "Info: 5: + IC(0.262 ns) + CELL(0.149 ns) = 2.242 ns; Loc. = LCCOMB_X59_Y26_N16; Fanout = 2; COMB Node = 'clock:inst\|Add4~496'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.411 ns" { clock:inst|Add4~495 clock:inst|Add4~496 } "NODE_NAME" } } { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.271 ns) + CELL(0.414 ns) 2.927 ns clock:inst\|Add4~501 6 COMB LCCOMB_X59_Y26_N2 2 " "Info: 6: + IC(0.271 ns) + CELL(0.414 ns) = 2.927 ns; Loc. = LCCOMB_X59_Y26_N2; Fanout = 2; COMB Node = 'clock:inst\|Add4~501'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.685 ns" { clock:inst|Add4~496 clock:inst|Add4~501 } "NODE_NAME" } } { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.998 ns clock:inst\|Add4~504 7 COMB LCCOMB_X59_Y26_N4 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 2.998 ns; Loc. = LCCOMB_X59_Y26_N4; Fanout = 2; COMB Node = 'clock:inst\|Add4~504'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { clock:inst|Add4~501 clock:inst|Add4~504 } "NODE_NAME" } } { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 3.408 ns clock:inst\|Add4~506 8 COMB LCCOMB_X59_Y26_N6 1 " "Info: 8: + IC(0.000 ns) + CELL(0.410 ns) = 3.408 ns; Loc. = LCCOMB_X59_Y26_N6; Fanout = 1; COMB Node = 'clock:inst\|Add4~506'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { clock:inst|Add4~504 clock:inst|Add4~506 } "NODE_NAME" } } { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.275 ns) 4.134 ns clock:inst\|Add4~508 9 COMB LCCOMB_X60_Y26_N12 1 " "Info: 9: + IC(0.451 ns) + CELL(0.275 ns) = 4.134 ns; Loc. = LCCOMB_X60_Y26_N12; Fanout = 1; COMB Node = 'clock:inst\|Add4~508'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.726 ns" { clock:inst|Add4~506 clock:inst|Add4~508 } "NODE_NAME" } } { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 4.218 ns clock:inst\|h1\[3\] 10 REG LCFF_X60_Y26_N13 5 " "Info: 10: + IC(0.000 ns) + CELL(0.084 ns) = 4.218 ns; Loc. = LCFF_X60_Y26_N13; Fanout = 5; REG Node = 'clock:inst\|h1\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { clock:inst|Add4~508 clock:inst|h1[3] } "NODE_NAME" } } { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 103 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.978 ns ( 46.89 % ) " "Info: Total cell delay = 1.978 ns ( 46.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.240 ns ( 53.11 % ) " "Info: Total interconnect delay = 2.240 ns ( 53.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.218 ns" { clock:inst|s1[3] clock:inst|always2~202 clock:inst|always2~203 clock:inst|Add4~495 clock:inst|Add4~496 clock:inst|Add4~501 clock:inst|Add4~504 clock:inst|Add4~506 clock:inst|Add4~508 clock:inst|h1[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.218 ns" { clock:inst|s1[3] clock:inst|always2~202 clock:inst|always2~203 clock:inst|Add4~495 clock:inst|Add4~496 clock:inst|Add4~501 clock:inst|Add4~504 clock:inst|Add4~506 clock:inst|Add4~508 clock:inst|h1[3] } { 0.000ns 0.734ns 0.263ns 0.259ns 0.262ns 0.271ns 0.000ns 0.000ns 0.451ns 0.000ns } { 0.000ns 0.275ns 0.150ns 0.150ns 0.149ns 0.414ns 0.071ns 0.410ns 0.275ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.309 ns - Smallest " "Info: - Smallest clock skew is -0.309 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW\[2\] destination 9.511 ns + Shortest register " "Info: + Shortest clock path from clock \"SW\[2\]\" to destination register is 9.511 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns SW\[2\] 1 CLK PIN_P25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P25; Fanout = 2; CLK Node = 'SW\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SW[2] } "NODE_NAME" } } { "BB.bdf" "" { Schematic "E:/SOPClab/digital_system_design/multifunction_digital_clock/toplever/BB.bdf" { { 272 16 184 288 "SW\[1\]" "" } { 248 16 184 264 "SW\[2\]" "" } { 296 16 184 312 "SW\[0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.957 ns) + CELL(0.150 ns) 3.106 ns clock:inst\|funckey 2 COMB LCCOMB_X34_Y3_N6 1 " "Info: 2: + IC(1.957 ns) + CELL(0.150 ns) = 3.106 ns; Loc. = LCCOMB_X34_Y3_N6; Fanout = 1; COMB Node = 'clock:inst\|funckey'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.107 ns" { SW[2] clock:inst|funckey } "NODE_NAME" } } { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.731 ns) + CELL(0.000 ns) 3.837 ns clock:inst\|funckey~clkctrl 3 COMB CLKCTRL_G12 3 " "Info: 3: + IC(0.731 ns) + CELL(0.000 ns) = 3.837 ns; Loc. = CLKCTRL_G12; Fanout = 3; COMB Node = 'clock:inst\|funckey~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.731 ns" { clock:inst|funckey clock:inst|funckey~clkctrl } "NODE_NAME" } } { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.787 ns) 5.638 ns clock:inst\|mode\[0\] 4 REG LCFF_X59_Y22_N15 22 " "Info: 4: + IC(1.014 ns) + CELL(0.787 ns) = 5.638 ns; Loc. = LCFF_X59_Y22_N15; Fanout = 22; REG Node = 'clock:inst\|mode\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.801 ns" { clock:inst|funckey~clkctrl clock:inst|mode[0] } "NODE_NAME" } } { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.531 ns) + CELL(0.150 ns) 6.319 ns clock:inst\|Equal3~92 5 COMB LCCOMB_X60_Y22_N26 30 " "Info: 5: + IC(0.531 ns) + CELL(0.150 ns) = 6.319 ns; Loc. = LCCOMB_X60_Y22_N26; Fanout = 30; COMB Node = 'clock:inst\|Equal3~92'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.681 ns" { clock:inst|mode[0] clock:inst|Equal3~92 } "NODE_NAME" } } { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 230 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(0.150 ns) 6.728 ns clock:inst\|clk_1~143 6 COMB LCCOMB_X60_Y22_N24 1 " "Info: 6: + IC(0.259 ns) + CELL(0.150 ns) = 6.728 ns; Loc. = LCCOMB_X60_Y22_N24; Fanout = 1; COMB Node = 'clock:inst\|clk_1~143'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.409 ns" { clock:inst|Equal3~92 clock:inst|clk_1~143 } "NODE_NAME" } } { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.258 ns) + CELL(0.000 ns) 7.986 ns clock:inst\|clk_1~143clkctrl 7 COMB CLKCTRL_G6 20 " "Info: 7: + IC(1.258 ns) + CELL(0.000 ns) = 7.986 ns; Loc. = CLKCTRL_G6; Fanout = 20; COMB Node = 'clock:inst\|clk_1~143clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.258 ns" { clock:inst|clk_1~143 clock:inst|clk_1~143clkctrl } "NODE_NAME" } } { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.988 ns) + CELL(0.537 ns) 9.511 ns clock:inst\|h1\[3\] 8 REG LCFF_X60_Y26_N13 5 " "Info: 8: + IC(0.988 ns) + CELL(0.537 ns) = 9.511 ns; Loc. = LCFF_X60_Y26_N13; Fanout = 5; REG Node = 'clock:inst\|h1\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.525 ns" { clock:inst|clk_1~143clkctrl clock:inst|h1[3] } "NODE_NAME" } } { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 103 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.773 ns ( 29.16 % ) " "Info: Total cell delay = 2.773 ns ( 29.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.738 ns ( 70.84 % ) " "Info: Total interconnect delay = 6.738 ns ( 70.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.511 ns" { SW[2] clock:inst|funckey clock:inst|funckey~clkctrl clock:inst|mode[0] clock:inst|Equal3~92 clock:inst|clk_1~143 clock:inst|clk_1~143clkctrl clock:inst|h1[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.511 ns" { SW[2] SW[2]~combout clock:inst|funckey clock:inst|funckey~clkctrl clock:inst|mode[0] clock:inst|Equal3~92 clock:inst|clk_1~143 clock:inst|clk_1~143clkctrl clock:inst|h1[3] } { 0.000ns 0.000ns 1.957ns 0.731ns 1.014ns 0.531ns 0.259ns 1.258ns 0.988ns } { 0.000ns 0.999ns 0.150ns 0.000ns 0.787ns 0.150ns 0.150ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW\[2\] source 9.820 ns - Longest register " "Info: - Longest clock path from clock \"SW\[2\]\" to source register is 9.820 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns SW\[2\] 1 CLK PIN_P25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P25; Fanout = 2; CLK Node = 'SW\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SW[2] } "NODE_NAME" } } { "BB.bdf" "" { Schematic "E:/SOPClab/digital_system_design/multifunction_digital_clock/toplever/BB.bdf" { { 272 16 184 288 "SW\[1\]" "" } { 248 16 184 264 "SW\[2\]" "" } { 296 16 184 312 "SW\[0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.957 ns) + CELL(0.150 ns) 3.106 ns clock:inst\|funckey 2 COMB LCCOMB_X34_Y3_N6 1 " "Info: 2: + IC(1.957 ns) + CELL(0.150 ns) = 3.106 ns; Loc. = LCCOMB_X34_Y3_N6; Fanout = 1; COMB Node = 'clock:inst\|funckey'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.107 ns" { SW[2] clock:inst|funckey } "NODE_NAME" } } { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.731 ns) + CELL(0.000 ns) 3.837 ns clock:inst\|funckey~clkctrl 3 COMB CLKCTRL_G12 3 " "Info: 3: + IC(0.731 ns) + CELL(0.000 ns) = 3.837 ns; Loc. = CLKCTRL_G12; Fanout = 3; COMB Node = 'clock:inst\|funckey~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.731 ns" { clock:inst|funckey clock:inst|funckey~clkctrl } "NODE_NAME" } } { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.787 ns) 5.638 ns clock:inst\|mode\[2\] 4 REG LCFF_X59_Y22_N1 22 " "Info: 4: + IC(1.014 ns) + CELL(0.787 ns) = 5.638 ns; Loc. = LCFF_X59_Y22_N1; Fanout = 22; REG Node = 'clock:inst\|mode\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.801 ns" { clock:inst|funckey~clkctrl clock:inst|mode[2] } "NODE_NAME" } } { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.554 ns) + CELL(0.438 ns) 6.630 ns clock:inst\|Equal3~92 5 COMB LCCOMB_X60_Y22_N26 30 " "Info: 5: + IC(0.554 ns) + CELL(0.438 ns) = 6.630 ns; Loc. = LCCOMB_X60_Y22_N26; Fanout = 30; COMB Node = 'clock:inst\|Equal3~92'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.992 ns" { clock:inst|mode[2] clock:inst|Equal3~92 } "NODE_NAME" } } { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 230 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(0.150 ns) 7.039 ns clock:inst\|clk_1~143 6 COMB LCCOMB_X60_Y22_N24 1 " "Info: 6: + IC(0.259 ns) + CELL(0.150 ns) = 7.039 ns; Loc. = LCCOMB_X60_Y22_N24; Fanout = 1; COMB Node = 'clock:inst\|clk_1~143'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.409 ns" { clock:inst|Equal3~92 clock:inst|clk_1~143 } "NODE_NAME" } } { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.258 ns) + CELL(0.000 ns) 8.297 ns clock:inst\|clk_1~143clkctrl 7 COMB CLKCTRL_G6 20 " "Info: 7: + IC(1.258 ns) + CELL(0.000 ns) = 8.297 ns; Loc. = CLKCTRL_G6; Fanout = 20; COMB Node = 'clock:inst\|clk_1~143clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.258 ns" { clock:inst|clk_1~143 clock:inst|clk_1~143clkctrl } "NODE_NAME" } } { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.986 ns) + CELL(0.537 ns) 9.820 ns clock:inst\|s1\[3\] 8 REG LCFF_X57_Y26_N25 8 " "Info: 8: + IC(0.986 ns) + CELL(0.537 ns) = 9.820 ns; Loc. = LCFF_X57_Y26_N25; Fanout = 8; REG Node = 'clock:inst\|s1\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.523 ns" { clock:inst|clk_1~143clkctrl clock:inst|s1[3] } "NODE_NAME" } } { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 103 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.061 ns ( 31.17 % ) " "Info: Total cell delay = 3.061 ns ( 31.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.759 ns ( 68.83 % ) " "Info: Total interconnect delay = 6.759 ns ( 68.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.820 ns" { SW[2] clock:inst|funckey clock:inst|funckey~clkctrl clock:inst|mode[2] clock:inst|Equal3~92 clock:inst|clk_1~143 clock:inst|clk_1~143clkctrl clock:inst|s1[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.820 ns" { SW[2] SW[2]~combout clock:inst|funckey clock:inst|funckey~clkctrl clock:inst|mode[2] clock:inst|Equal3~92 clock:inst|clk_1~143 clock:inst|clk_1~143clkctrl clock:inst|s1[3] } { 0.000ns 0.000ns 1.957ns 0.731ns 1.014ns 0.554ns 0.259ns 1.258ns 0.986ns } { 0.000ns 0.999ns 0.150ns 0.000ns 0.787ns 0.438ns 0.150ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.511 ns" { SW[2] clock:inst|funckey clock:inst|funckey~clkctrl clock:inst|mode[0] clock:inst|Equal3~92 clock:inst|clk_1~143 clock:inst|clk_1~143clkctrl clock:inst|h1[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.511 ns" { SW[2] SW[2]~combout clock:inst|funckey clock:inst|funckey~clkctrl clock:inst|mode[0] clock:inst|Equal3~92 clock:inst|clk_1~143 clock:inst|clk_1~143clkctrl clock:inst|h1[3] } { 0.000ns 0.000ns 1.957ns 0.731ns 1.014ns 0.531ns 0.259ns 1.258ns 0.988ns } { 0.000ns 0.999ns 0.150ns 0.000ns 0.787ns 0.150ns 0.150ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.820 ns" { SW[2] clock:inst|funckey clock:inst|funckey~clkctrl clock:inst|mode[2] clock:inst|Equal3~92 clock:inst|clk_1~143 clock:inst|clk_1~143clkctrl clock:inst|s1[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.820 ns" { SW[2] SW[2]~combout clock:inst|funckey clock:inst|funckey~clkctrl clock:inst|mode[2] clock:inst|Equal3~92 clock:inst|clk_1~143 clock:inst|clk_1~143clkctrl clock:inst|s1[3] } { 0.000ns 0.000ns 1.957ns 0.731ns 1.014ns 0.554ns 0.259ns 1.258ns 0.986ns } { 0.000ns 0.999ns 0.150ns 0.000ns 0.787ns 0.438ns 0.150ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 103 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 103 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.218 ns" { clock:inst|s1[3] clock:inst|always2~202 clock:inst|always2~203 clock:inst|Add4~495 clock:inst|Add4~496 clock:inst|Add4~501 clock:inst|Add4~504 clock:inst|Add4~506 clock:inst|Add4~508 clock:inst|h1[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.218 ns" { clock:inst|s1[3] clock:inst|always2~202 clock:inst|always2~203 clock:inst|Add4~495 clock:inst|Add4~496 clock:inst|Add4~501 clock:inst|Add4~504 clock:inst|Add4~506 clock:inst|Add4~508 clock:inst|h1[3] } { 0.000ns 0.734ns 0.263ns 0.259ns 0.262ns 0.271ns 0.000ns 0.000ns 0.451ns 0.000ns } { 0.000ns 0.275ns 0.150ns 0.150ns 0.149ns 0.414ns 0.071ns 0.410ns 0.275ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.511 ns" { SW[2] clock:inst|funckey clock:inst|funckey~clkctrl clock:inst|mode[0] clock:inst|Equal3~92 clock:inst|clk_1~143 clock:inst|clk_1~143clkctrl clock:inst|h1[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.511 ns" { SW[2] SW[2]~combout clock:inst|funckey clock:inst|funckey~clkctrl clock:inst|mode[0] clock:inst|Equal3~92 clock:inst|clk_1~143 clock:inst|clk_1~143clkctrl clock:inst|h1[3] } { 0.000ns 0.000ns 1.957ns 0.731ns 1.014ns 0.531ns 0.259ns 1.258ns 0.988ns } { 0.000ns 0.999ns 0.150ns 0.000ns 0.787ns 0.150ns 0.150ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.820 ns" { SW[2] clock:inst|funckey clock:inst|funckey~clkctrl clock:inst|mode[2] clock:inst|Equal3~92 clock:inst|clk_1~143 clock:inst|clk_1~143clkctrl clock:inst|s1[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.820 ns" { SW[2] SW[2]~combout clock:inst|funckey clock:inst|funckey~clkctrl clock:inst|mode[2] clock:inst|Equal3~92 clock:inst|clk_1~143 clock:inst|clk_1~143clkctrl clock:inst|s1[3] } { 0.000ns 0.000ns 1.957ns 0.731ns 1.014ns 0.554ns 0.259ns 1.258ns 0.986ns } { 0.000ns 0.999ns 0.150ns 0.000ns 0.787ns 0.438ns 0.150ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}