bb.map.qmsg

多功能电子钟

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(124) " "Warning (10230): Verilog HDL assignment warning at clock.v(124): truncated value with size 32 to match size of target (7)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 124 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(128) " "Warning (10230): Verilog HDL assignment warning at clock.v(128): truncated value with size 32 to match size of target (7)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 128 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(132) " "Warning (10230): Verilog HDL assignment warning at clock.v(132): truncated value with size 32 to match size of target (7)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 132 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 clock.v(135) " "Warning (10230): Verilog HDL assignment warning at clock.v(135): truncated value with size 32 to match size of target (8)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 135 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 clock.v(137) " "Warning (10230): Verilog HDL assignment warning at clock.v(137): truncated value with size 32 to match size of target (8)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 137 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(153) " "Warning (10230): Verilog HDL assignment warning at clock.v(153): truncated value with size 32 to match size of target (6)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 153 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(155) " "Warning (10230): Verilog HDL assignment warning at clock.v(155): truncated value with size 32 to match size of target (6)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 155 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(163) " "Warning (10230): Verilog HDL assignment warning at clock.v(163): truncated value with size 32 to match size of target (7)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 163 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(165) " "Warning (10230): Verilog HDL assignment warning at clock.v(165): truncated value with size 32 to match size of target (7)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 165 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 clock.v(181) " "Warning (10230): Verilog HDL assignment warning at clock.v(181): truncated value with size 32 to match size of target (5)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 181 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 clock.v(183) " "Warning (10230): Verilog HDL assignment warning at clock.v(183): truncated value with size 32 to match size of target (5)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 183 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(192) " "Warning (10230): Verilog HDL assignment warning at clock.v(192): truncated value with size 32 to match size of target (6)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 192 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(194) " "Warning (10230): Verilog HDL assignment warning at clock.v(194): truncated value with size 32 to match size of target (6)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 194 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(199) " "Warning (10230): Verilog HDL assignment warning at clock.v(199): truncated value with size 32 to match size of target (6)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 199 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(201) " "Warning (10230): Verilog HDL assignment warning at clock.v(201): truncated value with size 32 to match size of target (6)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 201 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(206) " "Warning (10230): Verilog HDL assignment warning at clock.v(206): truncated value with size 32 to match size of target (6)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 206 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(208) " "Warning (10230): Verilog HDL assignment warning at clock.v(208): truncated value with size 32 to match size of target (6)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 208 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fenpin1Hz fenpin1Hz:inst5 " "Info: Elaborating entity \"fenpin1Hz\" for hierarchy \"fenpin1Hz:inst5\"" {  } { { "BB.bdf" "inst5" { Schematic "E:/SOPClab/digital_system_design/multifunction_digital_clock/toplever/BB.bdf" { { 136 232 352 232 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fenpin1kHz fenpin1kHz:inst7 " "Info: Elaborating entity \"fenpin1kHz\" for hierarchy \"fenpin1kHz:inst7\"" {  } { { "BB.bdf" "inst7" { Schematic "E:/SOPClab/digital_system_design/multifunction_digital_clock/toplever/BB.bdf" { { 0 232 352 96 "inst7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "display1 display1:inst4 " "Info: Elaborating entity \"display1\" for hierarchy \"display1:inst4\"" {  } { { "BB.bdf" "inst4" { Schematic "E:/SOPClab/digital_system_design/multifunction_digital_clock/toplever/BB.bdf" { { 296 616 808 392 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "fenpin1kHz:inst7\|tout\[0\] fenpin1Hz:inst5\|tout\[0\] " "Info: Duplicate register \"fenpin1kHz:inst7\|tout\[0\]\" merged to single register \"fenpin1Hz:inst5\|tout\[0\]\"" {  } { { "../fenpin1kHz/fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 14 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "clock:inst\|mode\[3\] data_in GND " "Warning: Reduced register \"clock:inst\|mode\[3\]\" with stuck data_in port to stuck value GND" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "407 " "Info: Implemented 407 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "50 " "Info: Implemented 50 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "353 " "Info: Implemented 353 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 33 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 33 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 25 17:23:00 2009 " "Info: Processing ended: Wed Mar 25 17:23:00 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}