bb.map.qmsg

多功能电子钟

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 25 17:22:54 2009 " "Info: Processing started: Wed Mar 25 17:22:54 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off BB -c BB " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off BB -c BB" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../fenpin1kHz/fenpin1kHz.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../fenpin1kHz/fenpin1kHz.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fenpin1kHz-behav " "Info: Found design unit 1: fenpin1kHz-behav" {  } { { "../fenpin1kHz/fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fenpin1kHz " "Info: Found entity 1: fenpin1kHz" {  } { { "../fenpin1kHz/fenpin1kHz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1kHz/fenpin1kHz.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../display/display.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../display/display.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 display-behav " "Info: Found design unit 1: display-behav" {  } { { "../display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/display/display.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 display " "Info: Found entity 1: display" {  } { { "../display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/display/display.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../fenpin1Hz/fenpin1Hz.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../fenpin1Hz/fenpin1Hz.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fenpin1Hz-behav " "Info: Found design unit 1: fenpin1Hz-behav" {  } { { "../fenpin1Hz/fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fenpin1Hz " "Info: Found entity 1: fenpin1Hz" {  } { { "../fenpin1Hz/fenpin1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/fenpin1Hz/fenpin1Hz.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../display1/display1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../display1/display1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 display1-behav " "Info: Found design unit 1: display1-behav" {  } { { "../display1/display1.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/display1/display1.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 display1 " "Info: Found entity 1: display1" {  } { { "../display1/display1.vhd" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/display1/display1.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../clock/clock.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../clock/clock.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "E:/SOPClab/digital_system_design/multifunction_digital_clock/BB/BB.bdf " "Warning: Can't analyze file -- file E:/SOPClab/digital_system_design/multifunction_digital_clock/BB/BB.bdf is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "BB.bdf 1 1 " "Warning: Using design file BB.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 BB " "Info: Found entity 1: BB" {  } { { "BB.bdf" "" { Schematic "E:/SOPClab/digital_system_design/multifunction_digital_clock/toplever/BB.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "BB " "Info: Elaborating entity \"BB\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "display display:inst6 " "Info: Elaborating entity \"display\" for hierarchy \"display:inst6\"" {  } { { "BB.bdf" "inst6" { Schematic "E:/SOPClab/digital_system_design/multifunction_digital_clock/toplever/BB.bdf" { { -40 616 808 56 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock clock:inst " "Info: Elaborating entity \"clock\" for hierarchy \"clock:inst\"" {  } { { "BB.bdf" "inst" { Schematic "E:/SOPClab/digital_system_design/multifunction_digital_clock/toplever/BB.bdf" { { 136 392 552 264 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 clock.v(34) " "Warning (10230): Verilog HDL assignment warning at clock.v(34): truncated value with size 32 to match size of target (3)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 34 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(45) " "Warning (10230): Verilog HDL assignment warning at clock.v(45): truncated value with size 32 to match size of target (4)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 45 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(64) " "Warning (10230): Verilog HDL assignment warning at clock.v(64): truncated value with size 32 to match size of target (6)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 64 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(69) " "Warning (10230): Verilog HDL assignment warning at clock.v(69): truncated value with size 32 to match size of target (6)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 69 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(73) " "Warning (10230): Verilog HDL assignment warning at clock.v(73): truncated value with size 32 to match size of target (7)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 73 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(77) " "Warning (10230): Verilog HDL assignment warning at clock.v(77): truncated value with size 32 to match size of target (7)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 77 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(80) " "Warning (10230): Verilog HDL assignment warning at clock.v(80): truncated value with size 32 to match size of target (7)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 80 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(82) " "Warning (10230): Verilog HDL assignment warning at clock.v(82): truncated value with size 32 to match size of target (7)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 82 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(90) " "Warning (10230): Verilog HDL assignment warning at clock.v(90): truncated value with size 32 to match size of target (6)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 90 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(92) " "Warning (10230): Verilog HDL assignment warning at clock.v(92): truncated value with size 32 to match size of target (6)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 92 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(99) " "Warning (10230): Verilog HDL assignment warning at clock.v(99): truncated value with size 32 to match size of target (7)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 99 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(101) " "Warning (10230): Verilog HDL assignment warning at clock.v(101): truncated value with size 32 to match size of target (7)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 101 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(119) " "Warning (10230): Verilog HDL assignment warning at clock.v(119): truncated value with size 32 to match size of target (7)" {  } { { "../clock/clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 119 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}