bb.map.rpt

多功能电子钟

;    |display:inst6|         ; 6 (6)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |BB|display:inst6    ;
;    |fenpin1Hz:inst5|       ; 46 (46)           ; 26 (26)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |BB|fenpin1Hz:inst5  ;
;    |fenpin1kHz:inst7|      ; 25 (25)           ; 15 (15)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |BB|fenpin1kHz:inst7 ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+----------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 117   ;
; Number of registers using Synchronous Clear  ; 11    ;
; Number of registers using Synchronous Load   ; 5     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 17    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 6:1                ; 2 bits    ; 8 LEs         ; 2 LEs                ; 6 LEs                  ; Yes        ; |BB|clock:inst|m2[6]       ;
; 6:1                ; 4 bits    ; 16 LEs        ; 4 LEs                ; 12 LEs                 ; Yes        ; |BB|clock:inst|day[2]      ;
; 7:1                ; 5 bits    ; 20 LEs        ; 5 LEs                ; 15 LEs                 ; Yes        ; |BB|clock:inst|h1[5]       ;
; 9:1                ; 5 bits    ; 30 LEs        ; 5 LEs                ; 25 LEs                 ; Yes        ; |BB|clock:inst|m1[3]       ;
; 3:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; No         ; |BB|clock:inst|second[2]   ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |BB|clock:inst|minute[6]   ;
; 4:1                ; 11 bits   ; 22 LEs        ; 22 LEs               ; 0 LEs                  ; No         ; |BB|clock:inst|hour[0]     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+------------------------------------------+
; Source assignments for fenpin1Hz:inst5   ;
+----------------+-------+------+----------+
; Assignment     ; Value ; From ; To       ;
+----------------+-------+------+----------+
; POWER_UP_LEVEL ; Low   ; -    ; tout[1]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[0]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[2]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[3]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[4]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[5]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[6]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[7]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[8]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[9]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[10] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[11] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[12] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[13] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[14] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[15] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[16] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[17] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[18] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[19] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[20] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[21] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[22] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[23] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[24] ;
+----------------+-------+------+----------+


+------------------------------------------+
; Source assignments for fenpin1kHz:inst7  ;
+----------------+-------+------+----------+
; Assignment     ; Value ; From ; To       ;
+----------------+-------+------+----------+
; POWER_UP_LEVEL ; Low   ; -    ; tout[0]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[1]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[2]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[3]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[4]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[5]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[6]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[7]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[8]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[9]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[10] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[11] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[12] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[13] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[14] ;
+----------------+-------+------+----------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Mar 25 17:22:54 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off BB -c BB
Info: Found 2 design units, including 1 entities, in source file ../fenpin1kHz/fenpin1kHz.vhd
    Info: Found design unit 1: fenpin1kHz-behav
    Info: Found entity 1: fenpin1kHz
Info: Found 2 design units, including 1 entities, in source file ../display/display.vhd
    Info: Found design unit 1: display-behav
    Info: Found entity 1: display
Info: Found 2 design units, including 1 entities, in source file ../fenpin1Hz/fenpin1Hz.vhd
    Info: Found design unit 1: fenpin1Hz-behav
    Info: Found entity 1: fenpin1Hz
Info: Found 2 design units, including 1 entities, in source file ../display1/display1.vhd
    Info: Found design unit 1: display1-behav
    Info: Found entity 1: display1
Info: Found 1 design units, including 1 entities, in source file ../clock/clock.v
    Info: Found entity 1: clock
Warning: Can't analyze file -- file E:/SOPClab/digital_system_design/multifunction_digital_clock/BB/BB.bdf is missing
Warning: Using design file BB.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: BB
Info: Elaborating entity "BB" for the top level hierarchy
Info: Elaborating entity "display" for hierarchy "display:inst6"
Info: Elaborating entity "clock" for hierarchy "clock:inst"
Warning (10230): Verilog HDL assignment warning at clock.v(34): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at clock.v(45): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at clock.v(64): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at clock.v(69): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at clock.v(73): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at clock.v(77): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at clock.v(80): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at clock.v(82): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at clock.v(90): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at clock.v(92): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at clock.v(99): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at clock.v(101): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at clock.v(119): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at clock.v(124): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at clock.v(128): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at clock.v(132): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at clock.v(135): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at clock.v(137): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at clock.v(153): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at clock.v(155): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at clock.v(163): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at clock.v(165): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at clock.v(181): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at clock.v(183): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at clock.v(192): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at clock.v(194): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at clock.v(199): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at clock.v(201): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at clock.v(206): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at clock.v(208): truncated value with size 32 to match size of target (6)
Info: Elaborating entity "fenpin1Hz" for hierarchy "fenpin1Hz:inst5"
Info: Elaborating entity "fenpin1kHz" for hierarchy "fenpin1kHz:inst7"
Info: Elaborating entity "display1" for hierarchy "display1:inst4"
Info: Duplicate registers merged to single register
    Info: Duplicate register "fenpin1kHz:inst7|tout[0]" merged to single register "fenpin1Hz:inst5|tout[0]"
Warning: Reduced register "clock:inst|mode[3]" with stuck data_in port to stuck value GND
Info: Implemented 407 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 50 output pins
    Info: Implemented 353 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 33 warnings
    Info: Processing ended: Wed Mar 25 17:23:00 2009
    Info: Elapsed time: 00:00:07