clock.map.qmsg

多功能电子钟

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 25 09:42:48 2009 " "Info: Processing started: Wed Mar 25 09:42:48 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock -c clock --generate_symbol=E:\\SOPClab\\digital_system_design\\multifunction_digital_clock\\clock\\clock.v " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock --generate_symbol=E:\\SOPClab\\digital_system_design\\multifunction_digital_clock\\clock\\clock.v" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_EXTRA_SLASH_STAR" "clock.v(191) " "Warning (10090): Verilog HDL syntax warning at clock.v(191): extra block comment delimiter characters /* within block comment" {  } { { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 191 0 0 } }  } 0 10090 "Verilog HDL syntax warning at %1!s!: extra block comment delimiter characters /* within block comment" 0 0}
{ "Warning" "WVRFX_VERI_EXTRA_SLASH_STAR" "clock.v(218) " "Warning (10090): Verilog HDL syntax warning at clock.v(218): extra block comment delimiter characters /* within block comment" {  } { { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 218 0 0 } }  } 0 10090 "Verilog HDL syntax warning at %1!s!: extra block comment delimiter characters /* within block comment" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 25 09:42:48 2009 " "Info: Processing ended: Wed Mar 25 09:42:48 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}