clock.tan.qmsg

多功能电子钟

{ "Info" "ITDB_FULL_TCO_RESULT" "clk_1kHz mode\[0\] mode\[0\]~reg0 8.404 ns register " "Info: tco from clock \"clk_1kHz\" to destination pin \"mode\[0\]\" through register \"mode\[0\]~reg0\" is 8.404 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1kHz source 4.968 ns + Longest register " "Info: + Longest clock path from clock \"clk_1kHz\" to source register is 4.968 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.842 ns) 0.842 ns clk_1kHz 1 CLK PIN_R3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_R3; Fanout = 1; CLK Node = 'clk_1kHz'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_1kHz } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.925 ns) + CELL(0.787 ns) 2.554 ns temp1 2 REG LCFF_X1_Y18_N13 1 " "Info: 2: + IC(0.925 ns) + CELL(0.787 ns) = 2.554 ns; Loc. = LCFF_X1_Y18_N13; Fanout = 1; REG Node = 'temp1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.712 ns" { clk_1kHz temp1 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 2.877 ns funckey 3 COMB LCCOMB_X1_Y18_N12 1 " "Info: 3: + IC(0.000 ns) + CELL(0.323 ns) = 2.877 ns; Loc. = LCCOMB_X1_Y18_N12; Fanout = 1; COMB Node = 'funckey'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.323 ns" { temp1 funckey } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.571 ns) + CELL(0.000 ns) 3.448 ns funckey~clkctrl 4 COMB CLKCTRL_G2 3 " "Info: 4: + IC(0.571 ns) + CELL(0.000 ns) = 3.448 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'funckey~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.571 ns" { funckey funckey~clkctrl } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.983 ns) + CELL(0.537 ns) 4.968 ns mode\[0\]~reg0 5 REG LCFF_X1_Y10_N19 4 " "Info: 5: + IC(0.983 ns) + CELL(0.537 ns) = 4.968 ns; Loc. = LCFF_X1_Y10_N19; Fanout = 4; REG Node = 'mode\[0\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.520 ns" { funckey~clkctrl mode[0]~reg0 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.489 ns ( 50.10 % ) " "Info: Total cell delay = 2.489 ns ( 50.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.479 ns ( 49.90 % ) " "Info: Total interconnect delay = 2.479 ns ( 49.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.968 ns" { clk_1kHz temp1 funckey funckey~clkctrl mode[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.968 ns" { clk_1kHz clk_1kHz~combout temp1 funckey funckey~clkctrl mode[0]~reg0 } { 0.000ns 0.000ns 0.925ns 0.000ns 0.571ns 0.983ns } { 0.000ns 0.842ns 0.787ns 0.323ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.186 ns + Longest register pin " "Info: + Longest register to pin delay is 3.186 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mode\[0\]~reg0 1 REG LCFF_X1_Y10_N19 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y10_N19; Fanout = 4; REG Node = 'mode\[0\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { mode[0]~reg0 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.524 ns) + CELL(2.662 ns) 3.186 ns mode\[0\] 2 PIN PIN_W1 0 " "Info: 2: + IC(0.524 ns) + CELL(2.662 ns) = 3.186 ns; Loc. = PIN_W1; Fanout = 0; PIN Node = 'mode\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.186 ns" { mode[0]~reg0 mode[0] } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.662 ns ( 83.55 % ) " "Info: Total cell delay = 2.662 ns ( 83.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.524 ns ( 16.45 % ) " "Info: Total interconnect delay = 0.524 ns ( 16.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.186 ns" { mode[0]~reg0 mode[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.186 ns" { mode[0]~reg0 mode[0] } { 0.000ns 0.524ns } { 0.000ns 2.662ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.968 ns" { clk_1kHz temp1 funckey funckey~clkctrl mode[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.968 ns" { clk_1kHz clk_1kHz~combout temp1 funckey funckey~clkctrl mode[0]~reg0 } { 0.000ns 0.000ns 0.925ns 0.000ns 0.571ns 0.983ns } { 0.000ns 0.842ns 0.787ns 0.323ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.186 ns" { mode[0]~reg0 mode[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.186 ns" { mode[0]~reg0 mode[0] } { 0.000ns 0.524ns } { 0.000ns 2.662ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "temp1 func_key clk_1kHz -3.373 ns register " "Info: th for register \"temp1\" (data pin = \"func_key\", clock pin = \"clk_1kHz\") is -3.373 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1kHz destination 2.304 ns + Longest register " "Info: + Longest clock path from clock \"clk_1kHz\" to destination register is 2.304 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.842 ns) 0.842 ns clk_1kHz 1 CLK PIN_R3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_R3; Fanout = 1; CLK Node = 'clk_1kHz'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/w