clock.tan.qmsg

多功能电子钟

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk_1kHz register register mode\[0\]~reg0 mode\[1\]~reg0 450.05 MHz Internal " "Info: Clock \"clk_1kHz\" Internal fmax is restricted to 450.05 MHz between source register \"mode\[0\]~reg0\" and destination register \"mode\[1\]~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.222 ns " "Info: fmax restricted to clock pin edge rate 2.222 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.825 ns + Longest register register " "Info: + Longest register to register delay is 0.825 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mode\[0\]~reg0 1 REG LCFF_X1_Y10_N19 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y10_N19; Fanout = 4; REG Node = 'mode\[0\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { mode[0]~reg0 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.321 ns) + CELL(0.420 ns) 0.741 ns mode\[1\]~154 2 COMB LCCOMB_X1_Y10_N22 1 " "Info: 2: + IC(0.321 ns) + CELL(0.420 ns) = 0.741 ns; Loc. = LCCOMB_X1_Y10_N22; Fanout = 1; COMB Node = 'mode\[1\]~154'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.741 ns" { mode[0]~reg0 mode[1]~154 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.825 ns mode\[1\]~reg0 3 REG LCFF_X1_Y10_N23 3 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.825 ns; Loc. = LCFF_X1_Y10_N23; Fanout = 3; REG Node = 'mode\[1\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { mode[1]~154 mode[1]~reg0 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.504 ns ( 61.09 % ) " "Info: Total cell delay = 0.504 ns ( 61.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.321 ns ( 38.91 % ) " "Info: Total interconnect delay = 0.321 ns ( 38.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.825 ns" { mode[0]~reg0 mode[1]~154 mode[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.825 ns" { mode[0]~reg0 mode[1]~154 mode[1]~reg0 } { 0.000ns 0.321ns 0.000ns } { 0.000ns 0.420ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1kHz destination 4.968 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_1kHz\" to destination register is 4.968 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.842 ns) 0.842 ns clk_1kHz 1 CLK PIN_R3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_R3; Fanout = 1; CLK Node = 'clk_1kHz'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_1kHz } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.925 ns) + CELL(0.787 ns) 2.554 ns temp1 2 REG LCFF_X1_Y18_N13 1 " "Info: 2: + IC(0.925 ns) + CELL(0.787 ns) = 2.554 ns; Loc. = LCFF_X1_Y18_N13; Fanout = 1; REG Node = 'temp1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.712 ns" { clk_1kHz temp1 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 2.877 ns funckey 3 COMB LCCOMB_X1_Y18_N12 1 " "Info: 3: + IC(0.000 ns) + CELL(0.323 ns) = 2.877 ns; Loc. = LCCOMB_X1_Y18_N12; Fanout = 1; COMB Node = 'funckey'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.323 ns" { temp1 funckey } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.571 ns) + CELL(0.000 ns) 3.448 ns funckey~clkctrl 4 COMB CLKCTRL_G2 3 " "Info: 4: + IC(0.571 ns) + CELL(0.000 ns) = 3.448 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'funckey~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.571 ns" { funckey funckey~clkctrl } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.983 ns) + CELL(0.537 ns) 4.968 ns mode\[1\]~reg0 5 REG LCFF_X1_Y10_N23 3 " "Info: 5: + IC(0.983 ns) + CELL(0.537 ns) = 4.968 ns; Loc. = LCFF_X1_Y10_N23; Fanout = 3; REG Node = 'mode\[1\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.520 ns" { funckey~clkctrl mode[1]~reg0 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.489 ns ( 50.10 % ) " "Info: Total cell delay = 2.489 ns ( 50.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.479 ns ( 49.90 % ) " "Info: Total interconnect delay = 2.479 ns ( 49.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.968 ns" { clk_1kHz temp1 funckey funckey~clkctrl mode[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.968 ns" { clk_1kHz clk_1kHz~combout temp1 funckey funckey~clkctrl mode[1]~reg0 } { 0.000ns 0.000ns 0.925ns 0.000ns 0.571ns 0.983ns } { 0.000ns 0.842ns 0.787ns 0.323ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1kHz source 4.968 ns - Longest register " "Info: - Longest clock path from clock \"clk_1kHz\" to source register is 4.968 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.842 ns) 0.842 ns clk_1kHz 1 CLK PIN_R3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_R3; Fanout = 1; CLK Node = 'clk_1kHz'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_1kHz } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.925 ns) + CELL(0.787 ns) 2.554 ns temp1 2 REG LCFF_X1_Y18_N13 1 " "Info: 2: + IC(0.925 ns) + CELL(0.787 ns) = 2.554 ns; Loc. = LCFF_X1_Y18_N13; Fanout = 1; REG Node = 'temp1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.712 ns" { clk_1kHz temp1 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 2.877 ns funckey 3 COMB LCCOMB_X1_Y18_N12 1 " "Info: 3: + IC(0.000 ns) + CELL(0.323 ns) = 2.877 ns; Loc. = LCCOMB_X1_Y18_N12; Fanout = 1; COMB Node = 'funckey'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.323 ns" { temp1 funckey } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.571 ns) + CELL(0.000 ns) 3.448 ns funckey~clkctrl 4 COMB CLKCTRL_G2 3 " "Info: 4: + IC(0.571 ns) + CELL(0.000 ns) = 3.448 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'funckey~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.571 ns" { funckey funckey~clkctrl } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.983 ns) + CELL(0.537 ns) 4.968 ns mode\[0\]~reg0 5 REG LCFF_X1_Y10_N19 4 " "Info: 5: + IC(0.983 ns) + CELL(0.537 ns) = 4.968 ns; Loc. = LCFF_X1_Y10_N19; Fanout = 4; REG Node = 'mode\[0\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.520 ns" { funckey~clkctrl mode[0]~reg0 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.489 ns ( 50.10 % ) " "Info: Total cell delay = 2.489 ns ( 50.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.479 ns ( 49.90 % ) " "Info: Total interconnect delay = 2.479 ns ( 49.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.968 ns" { clk_1kHz temp1 funckey funckey~clkctrl mode[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.968 ns" { clk_1kHz clk_1kHz~combout temp1 funckey funckey~clkctrl mode[0]~reg0 } { 0.000ns 0.000ns 0.925ns 0.000ns 0.571ns 0.983ns } { 0.000ns 0.842ns 0.787ns 0.323ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.968 ns" { clk_1kHz temp1 funckey funckey~clkctrl mode[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.968 ns" { clk_1kHz clk_1kHz~combout temp1 funckey funckey~clkctrl mode[1]~reg0 } { 0.000ns 0.000ns 0.925ns 0.000ns 0.571ns 0.983ns } { 0.000ns 0.842ns 0.787ns 0.323ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.968 ns" { clk_1kHz temp1 funckey funckey~clkctrl mode[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.968 ns" { clk_1kHz clk_1kHz~combout temp1 funckey funckey~clkctrl mode[0]~reg0 } { 0.000ns 0.000ns 0.925ns 0.000ns 0.571ns 0.983ns } { 0.000ns 0.842ns 0.787ns 0.323ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.825 ns" { mode[0]~reg0 mode[1]~154 mode[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.825 ns" { mode[0]~reg0 mode[1]~154 mode[1]~reg0 } { 0.000ns 0.321ns 0.000ns } { 0.000ns 0.420ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.968 ns" { clk_1kHz temp1 funckey funckey~clkctrl mode[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.968 ns" { clk_1kHz clk_1kHz~combout temp1 funckey funckey~clkctrl mode[1]~reg0 } { 0.000ns 0.000ns 0.925ns 0.000ns 0.571ns 0.983ns } { 0.000ns 0.842ns 0.787ns 0.323ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.968 ns" { clk_1kHz temp1 funckey funckey~clkctrl mode[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.968 ns" { clk_1kHz clk_1kHz~combout temp1 funckey funckey~clkctrl mode[0]~reg0 } { 0.000ns 0.000ns 0.925ns 0.000ns 0.571ns 0.983ns } { 0.000ns 0.842ns 0.787ns 0.323ns 0.000ns 0.537ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { mode[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { mode[1]~reg0 } {  } {  } } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_1Hz register second\[4\]~reg0 register hour\[7\]~reg0 245.64 MHz 4.071 ns Internal " "Info: Clock \"clk_1Hz\" has Internal fmax of 245.64 MHz between source register \"second\[4\]~reg0\" and destination register \"hour\[7\]~reg0\" (period= 4.071 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.859 ns + Longest register register " "Info: + Longest register to register delay is 3.859 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns second\[4\]~reg0 1 REG LCFF_X19_Y32_N1 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y32_N1; Fanout = 6; REG Node = 'second\[4\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { second[4]~reg0 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 99 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.503 ns) + CELL(0.410 ns) 0.913 ns minute~1429 2 COMB LCCOMB_X20_Y32_N0 8 " "Info: 2: + IC(0.503 ns) + CELL(0.410 ns) = 0.913 ns; Loc. = LCCOMB_X20_Y32_N0; Fanout = 8; COMB Node = 'minute~1429'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.913 ns" { second[4]~reg0 minute~1429 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.247 ns) + CELL(0.150 ns) 1.310 ns always2~205 3 COMB LCCOMB_X20_Y32_N30 18 " "Info: 3: + IC(0.247 ns) + CELL(0.150 ns) = 1.310 ns; Loc. = LCCOMB_X20_Y32_N30; Fanout = 18; COMB Node = 'always2~205'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.397 ns" { minute~1429 always2~205 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.273 ns) + CELL(0.150 ns) 1.733 ns always2~18 4 COMB LCCOMB_X20_Y32_N28 4 " "Info: 4: + IC(0.273 ns) + CELL(0.150 ns) = 1.733 ns; Loc. = LCCOMB_X20_Y32_N28; Fanout = 4; COMB Node = 'always2~18'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.423 ns" { always2~205 always2~18 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.265 ns) + CELL(0.393 ns) 2.391 ns Add1~148 5 COMB LCCOMB_X20_Y32_N8 2 " "Info: 5: + IC(0.265 ns) + CELL(0.393 ns) = 2.391 ns; Loc. = LCCOMB_X20_Y32_N8; Fanout = 2; COMB Node = 'Add1~148'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.658 ns" { always2~18 Add1~148 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.462 ns Add1~150 6 COMB LCCOMB_X20_Y32_N10 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 2.462 ns; Loc. = LCCOMB_X20_Y32_N10; Fanout = 2; COMB Node = 'Add1~150'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add1~148 Add1~150 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.533 ns Add1~152 7 COMB LCCOMB_X20_Y32_N12 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 2.533 ns; Loc. = LCCOMB_X20_Y32_N12; Fanout = 2; COMB Node = 'Add1~152'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add1~150 Add1~152 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 2.692 ns Add1~154 8 COMB LCCOMB_X20_Y32_N14 2 " "Info: 8: + IC(0.000 ns) + CELL(0.159 ns) = 2.692 ns; Loc. = LCCOMB_X20_Y32_N14; Fanout = 2; COMB Node = 'Add1~154'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.159 ns" { Add1~152 Add1~154 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.763 ns Add1~156 9 COMB LCCOMB_X20_Y32_N16 2 " "Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 2.763 ns; Loc. = LCCOMB_X20_Y32_N16; Fanout = 2; COMB Node = 'Add1~156'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add1~154 Add1~156 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.834 ns Add1~158 10 COMB LCCOMB_X20_Y32_N18 1 " "Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 2.834 ns; Loc. = LCCOMB_X20_Y32_N18; Fanout = 1; COMB Node = 'Add1~158'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add1~156 Add1~158 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 3.244 ns Add1~159 11 COMB LCCOMB_X20_Y32_N20 1 " "Info: 11: + IC(0.000 ns) + CELL(0.410 ns) = 3.244 ns; Loc. = LCCOMB_X20_Y32_N20; Fanout = 1; COMB Node = 'Add1~159'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { Add1~158 Add1~159 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.256 ns) + CELL(0.275 ns) 3.775 ns hour~360 12 COMB LCCOMB_X20_Y32_N26 1 " "Info: 12: + IC(0.256 ns) + CELL(0.275 ns) = 3.775 ns; Loc. = LCCOMB_X20_Y32_N26; Fanout = 1; COMB Node = 'hour~360'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.531 ns" { Add1~159 hour~360 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.859 ns hour\[7\]~reg0 13 REG LCFF_X20_Y32_N27 2 " "Info: 13: + IC(0.000 ns) + CELL(0.084 ns) = 3.859 ns; Loc. = LCFF_X20_Y32_N27; Fanout = 2; REG Node = 'hour\[7\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { hour~360 hour[7]~reg0 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 99 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.315 ns ( 59.99 % ) " "Info: Total cell delay = 2.315 ns ( 59.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.544 ns ( 40.01 % ) " "Info: Total interconnect delay = 1.544 ns ( 40.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.859 ns" { second[4]~reg0 minute~1429 always2~205 always2~18 Add1~148 Add1~150 Add1~152 Add1~154 Add1~156 Add1~158 Add1~159 hour~360 hour[7]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.859 ns" { second[4]~reg0 minute~1429 always2~205 always2~18 Add1~148 Add1~150 Add1~152 Add1~154 Add1~156 Add1~158 Add1~159 hour~360 hour[7]~reg0 } { 0.000ns 0.503ns 0.247ns 0.273ns 0.265ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.256ns 0.000ns } { 0.000ns 0.410ns 0.150ns 0.150ns 0.393ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.410ns 0.275ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.002 ns - Smallest " "Info: - Smallest clock skew is 0.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1Hz destination 2.681 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_1Hz\" to destination register is 2.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk_1Hz 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk_1Hz'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_1Hz } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk_1Hz~clkctrl 2 COMB CLKCTRL_G3 23 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 23; COMB Node = 'clk_1Hz~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk_1Hz clk_1Hz~clkctrl } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.027 ns) + CELL(0.537 ns) 2.681 ns hour\[7\]~reg0 3 REG LCFF_X20_Y32_N27 2 " "Info: 3: + IC(1.027 ns) + CELL(0.537 ns) = 2.681 ns; Loc. = LCFF_X20_Y32_N27; Fanout = 2; REG Node = 'hour\[7\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.564 ns" { clk_1Hz~clkctrl hour[7]~reg0 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 99 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.29 % ) " "Info: Total cell delay = 1.536 ns ( 57.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.145 ns ( 42.71 % ) " "Info: Total interconnect delay = 1.145 ns ( 42.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.681 ns" { clk_1Hz clk_1Hz~clkctrl hour[7]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.681 ns" { clk_1Hz clk_1Hz~combout clk_1Hz~clkctrl hour[7]~reg0 } { 0.000ns 0.000ns 0.118ns 1.027ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1Hz source 2.679 ns - Longest register " "Info: - Longest clock path from clock \"clk_1Hz\" to source register is 2.679 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk_1Hz 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk_1Hz'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_1Hz } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk_1Hz~clkctrl 2 COMB CLKCTRL_G3 23 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 23; COMB Node = 'clk_1Hz~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk_1Hz clk_1Hz~clkctrl } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.025 ns) + CELL(0.537 ns) 2.679 ns second\[4\]~reg0 3 REG LCFF_X19_Y32_N1 6 " "Info: 3: + IC(1.025 ns) + CELL(0.537 ns) = 2.679 ns; Loc. = LCFF_X19_Y32_N1; Fanout = 6; REG Node = 'second\[4\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.562 ns" { clk_1Hz~clkctrl second[4]~reg0 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 99 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.33 % ) " "Info: Total cell delay = 1.536 ns ( 57.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.143 ns ( 42.67 % ) " "Info: Total interconnect delay = 1.143 ns ( 42.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.679 ns" { clk_1Hz clk_1Hz~clkctrl second[4]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.679 ns" { clk_1Hz clk_1Hz~combout clk_1Hz~clkctrl second[4]~reg0 } { 0.000ns 0.000ns 0.118ns 1.025ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.681 ns" { clk_1Hz clk_1Hz~clkctrl hour[7]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.681 ns" { clk_1Hz clk_1Hz~combout clk_1Hz~clkctrl hour[7]~reg0 } { 0.000ns 0.000ns 0.118ns 1.027ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.679 ns" { clk_1Hz clk_1Hz~clkctrl second[4]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.679 ns" { clk_1Hz clk_1Hz~combout clk_1Hz~clkctrl second[4]~reg0 } { 0.000ns 0.000ns 0.118ns 1.025ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 99 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 99 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.859 ns" { second[4]~reg0 minute~1429 always2~205 always2~18 Add1~148 Add1~150 Add1~152 Add1~154 Add1~156 Add1~158 Add1~159 hour~360 hour[7]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.859 ns" { second[4]~reg0 minute~1429 always2~205 always2~18 Add1~148 Add1~150 Add1~152 Add1~154 Add1~156 Add1~158 Add1~159 hour~360 hour[7]~reg0 } { 0.000ns 0.503ns 0.247ns 0.273ns 0.265ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.256ns 0.000ns } { 0.000ns 0.410ns 0.150ns 0.150ns 0.393ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.410ns 0.275ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.681 ns" { clk_1Hz clk_1Hz~clkctrl hour[7]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.681 ns" { clk_1Hz clk_1Hz~combout clk_1Hz~clkctrl hour[7]~reg0 } { 0.000ns 0.000ns 0.118ns 1.027ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.679 ns" { clk_1Hz clk_1Hz~clkctrl second[4]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.679 ns" { clk_1Hz clk_1Hz~combout clk_1Hz~clkctrl second[4]~reg0 } { 0.000ns 0.000ns 0.118ns 1.025ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "temp1 func_key clk_1kHz 3.603 ns register " "Info: tsu for register \"temp1\" (data pin = \"func_key\", clock pin = \"clk_1kHz\") is 3.603 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.943 ns + Longest pin register " "Info: + Longest pin to register delay is 5.943 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.842 ns) 0.842 ns func_key 1 CLK PIN_P4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_P4; Fanout = 2; CLK Node = 'func_key'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { func_key } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.735 ns) + CELL(0.366 ns) 5.943 ns temp1 2 REG LCFF_X1_Y18_N13 1 " "Info: 2: + IC(4.735 ns) + CELL(0.366 ns) = 5.943 ns; Loc. = LCFF_X1_Y18_N13; Fanout = 1; REG Node = 'temp1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.101 ns" { func_key temp1 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.208 ns ( 20.33 % ) " "Info: Total cell delay = 1.208 ns ( 20.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.735 ns ( 79.67 % ) " "Info: Total interconnect delay = 4.735 ns ( 79.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.943 ns" { func_key temp1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.943 ns" { func_key func_key~combout temp1 } { 0.000ns 0.000ns 4.735ns } { 0.000ns 0.842ns 0.366ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1kHz destination 2.304 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_1kHz\" to destination register is 2.304 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.842 ns) 0.842 ns clk_1kHz 1 CLK PIN_R3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_R3; Fanout = 1; CLK Node = 'clk_1kHz'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_1kHz } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.925 ns) + CELL(0.537 ns) 2.304 ns temp1 2 REG LCFF_X1_Y18_N13 1 " "Info: 2: + IC(0.925 ns) + CELL(0.537 ns) = 2.304 ns; Loc. = LCFF_X1_Y18_N13; Fanout = 1; REG Node = 'temp1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.462 ns" { clk_1kHz temp1 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.379 ns ( 59.85 % ) " "Info: Total cell delay = 1.379 ns ( 59.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.925 ns ( 40.15 % ) " "Info: Total interconnect delay = 0.925 ns ( 40.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.304 ns" { clk_1kHz temp1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.304 ns" { clk_1kHz clk_1kHz~combout temp1 } { 0.000ns 0.000ns 0.925ns } { 0.000ns 0.842ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.943 ns" { func_key temp1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.943 ns" { func_key func_key~combout temp1 } { 0.000ns 0.000ns 4.735ns } { 0.000ns 0.842ns 0.366ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.304 ns" { clk_1kHz temp1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.304 ns" { clk_1kHz clk_1kHz~combout temp1 } { 0.000ns 0.000ns 0.925ns } { 0.000ns 0.842ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}