clock.tan.qmsg

多功能电子钟

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "func_key " "Info: Assuming node \"func_key\" is an undefined clock" {  } { { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 5 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "func_key" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_1kHz " "Info: Assuming node \"clk_1kHz\" is an undefined clock" {  } { { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 4 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk_1kHz" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_1Hz " "Info: Assuming node \"clk_1Hz\" is an undefined clock" {  } { { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 3 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk_1Hz" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "temp1 " "Info: Detected ripple clock \"temp1\" as buffer" {  } { { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 19 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "temp1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "funckey " "Info: Detected gated clock \"funckey\" as buffer" {  } { { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 20 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "funckey" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "func_key register register mode\[0\]~reg0 mode\[1\]~reg0 450.05 MHz Internal " "Info: Clock \"func_key\" Internal fmax is restricted to 450.05 MHz between source register \"mode\[0\]~reg0\" and destination register \"mode\[1\]~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.222 ns " "Info: fmax restricted to clock pin edge rate 2.222 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.825 ns + Longest register register " "Info: + Longest register to register delay is 0.825 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mode\[0\]~reg0 1 REG LCFF_X1_Y10_N19 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y10_N19; Fanout = 4; REG Node = 'mode\[0\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { mode[0]~reg0 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.321 ns) + CELL(0.420 ns) 0.741 ns mode\[1\]~154 2 COMB LCCOMB_X1_Y10_N22 1 " "Info: 2: + IC(0.321 ns) + CELL(0.420 ns) = 0.741 ns; Loc. = LCCOMB_X1_Y10_N22; Fanout = 1; COMB Node = 'mode\[1\]~154'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.741 ns" { mode[0]~reg0 mode[1]~154 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.825 ns mode\[1\]~reg0 3 REG LCFF_X1_Y10_N23 3 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.825 ns; Loc. = LCFF_X1_Y10_N23; Fanout = 3; REG Node = 'mode\[1\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { mode[1]~154 mode[1]~reg0 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.504 ns ( 61.09 % ) " "Info: Total cell delay = 0.504 ns ( 61.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.321 ns ( 38.91 % ) " "Info: Total interconnect delay = 0.321 ns ( 38.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.825 ns" { mode[0]~reg0 mode[1]~154 mode[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.825 ns" { mode[0]~reg0 mode[1]~154 mode[1]~reg0 } { 0.000ns 0.321ns 0.000ns } { 0.000ns 0.420ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "func_key destination 4.024 ns + Shortest register " "Info: + Shortest clock path from clock \"func_key\" to destination register is 4.024 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.842 ns) 0.842 ns func_key 1 CLK PIN_P4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_P4; Fanout = 2; CLK Node = 'func_key'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { func_key } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.941 ns) + CELL(0.150 ns) 1.933 ns funckey 2 COMB LCCOMB_X1_Y18_N12 1 " "Info: 2: + IC(0.941 ns) + CELL(0.150 ns) = 1.933 ns; Loc. = LCCOMB_X1_Y18_N12; Fanout = 1; COMB Node = 'funckey'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.091 ns" { func_key funckey } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.571 ns) + CELL(0.000 ns) 2.504 ns funckey~clkctrl 3 COMB CLKCTRL_G2 3 " "Info: 3: + IC(0.571 ns) + CELL(0.000 ns) = 2.504 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'funckey~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.571 ns" { funckey funckey~clkctrl } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.983 ns) + CELL(0.537 ns) 4.024 ns mode\[1\]~reg0 4 REG LCFF_X1_Y10_N23 3 " "Info: 4: + IC(0.983 ns) + CELL(0.537 ns) = 4.024 ns; Loc. = LCFF_X1_Y10_N23; Fanout = 3; REG Node = 'mode\[1\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.520 ns" { funckey~clkctrl mode[1]~reg0 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.529 ns ( 38.00 % ) " "Info: Total cell delay = 1.529 ns ( 38.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.495 ns ( 62.00 % ) " "Info: Total interconnect delay = 2.495 ns ( 62.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.024 ns" { func_key funckey funckey~clkctrl mode[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.024 ns" { func_key func_key~combout funckey funckey~clkctrl mode[1]~reg0 } { 0.000ns 0.000ns 0.941ns 0.571ns 0.983ns } { 0.000ns 0.842ns 0.150ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "func_key source 4.024 ns - Longest register " "Info: - Longest clock path from clock \"func_key\" to source register is 4.024 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.842 ns) 0.842 ns func_key 1 CLK PIN_P4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_P4; Fanout = 2; CLK Node = 'func_key'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { func_key } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.941 ns) + CELL(0.150 ns) 1.933 ns funckey 2 COMB LCCOMB_X1_Y18_N12 1 " "Info: 2: + IC(0.941 ns) + CELL(0.150 ns) = 1.933 ns; Loc. = LCCOMB_X1_Y18_N12; Fanout = 1; COMB Node = 'funckey'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.091 ns" { func_key funckey } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.571 ns) + CELL(0.000 ns) 2.504 ns funckey~clkctrl 3 COMB CLKCTRL_G2 3 " "Info: 3: + IC(0.571 ns) + CELL(0.000 ns) = 2.504 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'funckey~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.571 ns" { funckey funckey~clkctrl } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.983 ns) + CELL(0.537 ns) 4.024 ns mode\[0\]~reg0 4 REG LCFF_X1_Y10_N19 4 " "Info: 4: + IC(0.983 ns) + CELL(0.537 ns) = 4.024 ns; Loc. = LCFF_X1_Y10_N19; Fanout = 4; REG Node = 'mode\[0\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.520 ns" { funckey~clkctrl mode[0]~reg0 } "NODE_NAME" } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.529 ns ( 38.00 % ) " "Info: Total cell delay = 1.529 ns ( 38.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.495 ns ( 62.00 % ) " "Info: Total interconnect delay = 2.495 ns ( 62.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.024 ns" { func_key funckey funckey~clkctrl mode[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.024 ns" { func_key func_key~combout funckey funckey~clkctrl mode[0]~reg0 } { 0.000ns 0.000ns 0.941ns 0.571ns 0.983ns } { 0.000ns 0.842ns 0.150ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.024 ns" { func_key funckey funckey~clkctrl mode[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.024 ns" { func_key func_key~combout funckey funckey~clkctrl mode[1]~reg0 } { 0.000ns 0.000ns 0.941ns 0.571ns 0.983ns } { 0.000ns 0.842ns 0.150ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.024 ns" { func_key funckey funckey~clkctrl mode[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.024 ns" { func_key func_key~combout funckey funckey~clkctrl mode[0]~reg0 } { 0.000ns 0.000ns 0.941ns 0.571ns 0.983ns } { 0.000ns 0.842ns 0.150ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.825 ns" { mode[0]~reg0 mode[1]~154 mode[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.825 ns" { mode[0]~reg0 mode[1]~154 mode[1]~reg0 } { 0.000ns 0.321ns 0.000ns } { 0.000ns 0.420ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.024 ns" { func_key funckey funckey~clkctrl mode[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.024 ns" { func_key func_key~combout funckey funckey~clkctrl mode[1]~reg0 } { 0.000ns 0.000ns 0.941ns 0.571ns 0.983ns } { 0.000ns 0.842ns 0.150ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.024 ns" { func_key funckey funckey~clkctrl mode[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.024 ns" { func_key func_key~combout funckey funckey~clkctrl mode[0]~reg0 } { 0.000ns 0.000ns 0.941ns 0.571ns 0.983ns } { 0.000ns 0.842ns 0.150ns 0.000ns 0.537ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { mode[1]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { mode[1]~reg0 } {  } {  } } } { "clock.v" "" { Text "E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v" 46 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}