clock.map.rpt

多功能电子钟

+--------------------------------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                   ;
+----------------------------------+-----------------+------------------------+----------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                               ;
+----------------------------------+-----------------+------------------------+----------------------------------------------------------------------------+
; ../clock.v                       ; yes             ; User Verilog HDL File  ; E:/SOPClab/digital_system_design/multifunction_digital_clock/clock/clock.v ;
+----------------------------------+-----------------+------------------------+----------------------------------------------------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+---------------------------------------------+---------+
; Resource                                    ; Usage   ;
+---------------------------------------------+---------+
; Estimated Total logic elements              ; 58      ;
; Total combinational functions               ; 58      ;
; Logic element usage by number of LUT inputs ;         ;
;     -- 4 input functions                    ; 23      ;
;     -- 3 input functions                    ; 12      ;
;     -- <=2 input functions                  ; 23      ;
;         -- Combinational cells for routing  ; 0       ;
; Logic elements by mode                      ;         ;
;     -- normal mode                          ; 44      ;
;     -- arithmetic mode                      ; 14      ;
; Total registers                             ; 27      ;
; I/O pins                                    ; 34      ;
; Maximum fan-out node                        ; clk_1Hz ;
; Maximum fan-out                             ; 23      ;
; Total fan-out                               ; 253     ;
; Average fan-out                             ; 2.13    ;
+---------------------------------------------+---------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                 ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
; |clock                     ; 58 (58)           ; 27 (27)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 34   ; 0            ; |clock              ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 27    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 2     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 6:1                ; 3 bits    ; 12 LEs        ; 3 LEs                ; 9 LEs                  ; Yes        ; |clock|minute[5]~reg0      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Mar 25 09:31:04 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock
Warning (10090): Verilog HDL syntax warning at clock.v(191): extra block comment delimiter characters /* within block comment
Warning (10090): Verilog HDL syntax warning at clock.v(218): extra block comment delimiter characters /* within block comment
Info: Found 1 design units, including 1 entities, in source file clock.v
    Info: Found entity 1: clock
Info: Elaborating entity "clock" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at clock.v(20): object "adjust_key1" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at clock.v(20): object "adjust_key2" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at clock.v(34): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at clock.v(45): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at clock.v(62): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at clock.v(67): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at clock.v(71): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at clock.v(75): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at clock.v(78): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at clock.v(80): truncated value with size 32 to match size of target (8)
Warning (10034): Output port "alarm" at clock.v(12) has no driver
Warning: Reduced register "mode[3]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "second[7]~reg0" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "mode[3]" stuck at GND
    Warning: Pin "second[7]" stuck at GND
    Warning: Pin "alarm" stuck at GND
Warning: Design contains 2 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "key1"
    Warning: No output dependent on input pin "key2"
Info: Implemented 93 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 29 output pins
    Info: Implemented 59 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 22 warnings
    Info: Processing ended: Wed Mar 25 09:31:05 2009
    Info: Elapsed time: 00:00:02