intvecs1.asm

dsp5000系列dma汇编代码完全可靠可用

;**********************************************************************
;*		 (C) COPYRIGHT TEXAS INSTRUMENTS, INC. 1996 				  *
;*																	  *
;*		Interrupt Vector Assignments for 'C54x						  *
;**********************************************************************
	.title "Interrupt Vectors Table Initialization"

	.mmregs
	.ref _c_int00
	.ref _DMAC2ISR

;**********************************************************************
;*	   Interrupt/TRAP vectors
;* 
;* Note that not all interupt names will apply to any given target.
;* This serves only as a multi-purpose example across the C54x family.
;* Consult the TI DSP Reference manual to determine which interrupts 
;*   apply to a given target.
;**********************************************************************
	.sect	".intvecs"
RESET: BD   _c_int00
	   NOP
	   NOP
NMI:   BD   NMI
	   NOP
	   NOP 	
SINT17_V:			; Software Interrupt #17 Vector
	BD		SINT17_V
	NOP
	NOP

SINT18_V:			; Software Interrupt #18 Vector
    BD      SINT18_V
	NOP
	NOP

SINT19_V:			; Software Interrupt #19 Vector
	BD      SINT19_V		
	NOP
	NOP

SINT20_V:			; Software Interrupt #20 Vector
	BD		SINT20_V
	NOP
	NOP

SINT21_V:			; Software Interrupt #21 Vector
	BD		SINT21_V
	NOP
	NOP

SINT22_V:			; Software Interrupt #22 Vector
	BD		SINT22_V
	NOP
	NOP

SINT23_V:			; Software Interrupt #23 Vector
	BD		SINT23_V
	NOP
	NOP

SINT24_V:			; Software Interrupt #24 Vector
	BD		SINT24_V
	NOP
	NOP

SINT25_V:			; Software Interrupt #25 Vector
	BD		SINT25_V
	NOP
	NOP

SINT26_V:			; Software Interrupt #26 Vector
	BD		SINT26_V
	NOP
	NOP

SINT27_V:			; Software Interrupt #27 Vector
	BD		SINT27_V
	NOP
	NOP

SINT28_V:			; Software Interrupt #28 Vector
	BD		SINT28_V
	NOP
	NOP

SINT29_V:			
	BD		SINT29_V
	NOP
	NOP

SINT30_V:			; Software Interrupt #30 Vector (reserved)
    BD      SINT30_V				; save Status before branch
	NOP
	NOP				; switch to stack-based addressing

INT0_V:				; External User Interrupt #0 Vector
SINT0_V:			; Software Interrupt #0 Vector
	B		$
	NOP
	NOP

INT1_V:				; External User Interrupt #1 Vector
SINT1_V:			; Software Interrupt #1 Vector
	B		$
	NOP
	NOP

INT2_V:				; External User Interrupt #2 Vector
SINT2_V:			; Software Interrupt #2 Vector
	B		$
	NOP
	NOP

TINT_V:				; Internal Timer Interrupt Vector
SINT3_V:			; Software Interrupt #3 Vector
	B		$
	NOP
	NOP

RINT0_V:			; Serial Port 0 Receive Interrupt Vector
BRINT0_V:			; Buffered Serial Port 0 Receive Interrupt Vector
SINT4_V:			; Software Interrupt #4 Vector
	B		$
	NOP
	NOP

XINT0_V:			; Serial Port 0 Transmit Interrupt Vector
BXINT0_V:			; Buffered Serial Port Transmit Interrupt Vector
SINT5_V:			; Software Interrupt #5 Vector
	B		$
	NOP
	NOP

RINT1_V:			; Serial Port 1 Receive Interrupt Vector
TRINT_V:			; TDM Serial Port Receive Interrupt
SINT6_V:			; Software Interrupt #6 Vector
	B		$
	NOP
	NOP

XINT1_V:			; Serial Port 1 Transmit Interrupt Vector
TXINT_V:			; TDM Serial Port Transmit Interrupt
SINT7_V:			; Software Interrupt #7 Vector
	B		$
	NOP
	NOP

INT3_V:				; External User Interrupt #3 Vector
SINT8_V:			; Software Interrupt #8 Vector
	B		$    
	NOP
	NOP

HPINT_V:			; HPI Interrupt Vector
SINT9_V:			; Software Interrupt #9 Vector
	B		$
	NOP
	NOP

BRINT1_V:			; Buffered Serial Port 1 Receive Interrupt Vector
SINT10_V:			; Software Interrupt #10 Vector
	B		_DMAC2ISR
	NOP
	NOP

BXINT1_V:			; Buffered Serial Port 1 Transmit Interrupt Vector
SINT11_V:			; Software Interrupt #11 Vector
	B		$
	NOP
	NOP

RESERVED_V:			; Reserved Interrupt Vectors
	B		$
	NOP
	NOP

	.end