📄 dmac2.asm
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DMA_CH3_ELEM_CNT .set 100h
DMA_CH3_NUM_FRM .set 1
DSYNC_REVT1 .set 0101b << 12
DMA3_CTR .set 5141h
.global _DMAC2ISR
.global _buffer,_frame
DMSA .set 55h ;Subbank Address Register
DMSDI .set 56h ;Subbank Access Register With Autoincrement
DXR11 .set 43h ;McBSP1 data transmit register
DRR11 .set 41h ;McBSP1 data receive register
DMGSA .set 24h ;global reload registers .. source addr
DMSRC3 .set 0Fh ;Subbank address for DMA3 source address register
DMPREC .set 54h ;DMA control
ST0 .set 06h
ST1 .set 07h
AL .set 08h
AH .set 09h
AG .set 0Ah
.sect "asmcode"
_DMAC2ISR
PSHM ST0 ;save context
PSHM ST1
PSHM AL
PSHM AH
PSHM AG
PSHM AR4
PSHM AR5
;First, determine which input frame has been completed...
STM #_frame,AR4 ;AR4 holds address of frame count (initialized in .c file)
ADDM #1,*AR4 ;increment frame count (next input frame)
CMPM *AR4,#3 ;Frame 3 ?
BC frame3,TC ;Frame 3
CMPM *AR4,#2 ;Frame 2 ?
BC frame2,TC ;Frame 2
frame1:
LD #_buffer,A
LD #_buffer,B
B send_output
frame2:
LD #_buffer+100h,A
LD #_buffer+100h,B
B send_output
frame3:
ST #0,*AR4
LD #_buffer+200h,A
LD #_buffer+200h,B
send_output:
BITF *(DMPREC), #0008h ;poll for DMA3 transfer complete
BC send_output, TC
STM #DMSRC3,DMSA ;program DMA3 registers
STLM B ,DMSDI ;source
STM #DXR11,DMSDI ;destination
STM #DMA_CH3_ELEM_CNT-1,DMSDI ;element count
STM #(DMA_CH3_NUM_FRM-1) | DSYNC_REVT1, DMSDI ;frame count
STM #DMA3_CTR, DMSDI ;DMA3 control
ORM #0008h, *(DMPREC)
POPM AR5 ;context restoration
POPM AR4
POPM AG
POPM AH
POPM AL
POPM ST1
POPM ST0
.if __far_mode
fret
.else
ret
.endif
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