bsp2.asm

dsp5000系列dma汇编代码完全可靠可用

                    
BSP             .set    1   ; 5402 DSK audio in/out codec uses McBSP1

; one of 8, 16, 32, or 64, in khz
SAMPLERATE      .set  8

 
    
    .mmregs

SPCR1_VAL       .set    0000h

SPCR2_VAL       .set    0200h
                                  
RCR1_VAL        .set    040h

RCR2_VAL        .set    000h

XCR1_VAL        .set    040h

XCR2_VAL        .set    000h

PCR_VAL         .set    0ch



;MCBSP0_TO_CODEC0 .set 0xFE
MCBSP1_TO_CODEC1 .set 0xFD
;CODEC1_FC_ON    .set 0x8
;CODEC0_FC_ON    .set 0x4
;CPLD_CTRL2      .set 0x4

* McBSP Memory Mapped Registers
SPSA0           .set    038h
SPSD0           .set    039h
DRR10           .set    021h
DXR10           .set    023h
SPSA1           .set    048h
SPSD1           .set    049h
DRR11           .set    041h
DXR11           .set    043h

* McBSP Subaddresed Registers
SPCR1           .set    00h
SPCR2           .set    01h
RCR1            .set    02h
RCR2            .set    03h
XCR1            .set    04h
XCR2            .set    05h
SRGR1           .set    06h
SRGR2           .set    07h
PCR             .set    0Eh

;; Choose appropriate sub-address registers and DRR/DXR

        .if BSP = 0
SPSA    .set SPSA0
SPSD    .set SPSD0
RDRR    .set    0x21            ; McBSP0 data receive register 1
RRDXR    .set    0x23           ; McBSP0 data transmit register 1
MCBSP_TO_CODEC .set MCBSP0_TO_CODEC0
IMASK   .set  (1 << 4)
        .endif
        .if BSP = 1
SPSA    .set SPSA1
SPSD    .set SPSD1
RDRR    .set    0x41            ; McBSP1 data receive register 1
RDXR    .set    0x43            ; McBSP1 data transmit register 1
MCBSP_TO_CODEC .set MCBSP1_TO_CODEC1
IMASK   .set  (1 << 10)
        .endif

WR_MCBSP_SUB_REG        .macro  addr,val
                        stm     addr,SPSA
                        nop
                        stm     val,SPSD
                        nop
                        .endm

RD_MCBSP_SUB_REG        .macro  addr,acc
                        stm     #:addr:,SPSA
                        nop
                        ldm     SPSD,acc
                        nop
                        nop
                        nop
                        .endm   

    .global _DSS_init, _AIC_INIT
    .text

;*************************************************************************
;*   audio_init:
;*************************************************************************
_DSS_init

 ;    PSHM  AR1
 ;    PSHM  AR6
 ;    PSHM  AR7
  ;   rsbx CPL
  ;   nop                 ; cpl latency
  ;   nop                 ; cpl latency
  ;   nop                 ; cpl latency

     ld   #0, DP              
     ssbx INTM      
     ssbx SXM  


     
 ;    WR_MCBSP_SUB_REG   SPCR1,#0h               ; reset McBSP0
 ;    WR_MCBSP_SUB_REG   SPCR2,#0h

     ;; write McBSP registers        
     WR_MCBSP_SUB_REG   RCR1,#RCR1_VAL
     WR_MCBSP_SUB_REG   RCR2,#RCR2_VAL
        
     WR_MCBSP_SUB_REG   XCR1,#XCR1_VAL
     WR_MCBSP_SUB_REG   XCR2,#XCR2_VAL
        
     WR_MCBSP_SUB_REG   PCR,#PCR_VAL
        
     WR_MCBSP_SUB_REG   SPCR1,#SPCR1_VAL
     WR_MCBSP_SUB_REG   SPCR2,#SPCR2_VAL

     ;; connect to appropriate source
  ;   portr CPLD_CTRL2, dss_tmp
  ;   andm #MCBSP1_TO_CODEC1, dss_tmp
   ;  portw dss_tmp, CPLD_CTRL2

     ;; set interrupts to come from serial ports not DMA
     ;; by clearing bits 6 and 7 in DMPREC
  ;   andm       #0ff3fh, 54h

     ;; clear xmit register -- why?
  ;   stm #0, RDXR

     ;; now enable McBSP transmit and receive
     WR_MCBSP_SUB_REG   SPCR1,#SPCR1_VAL | 1
     WR_MCBSP_SUB_REG   SPCR2,#SPCR2_VAL | 1 
     
  ;   ssbx  CPL
  ;   POPM  AR7
  ;   POPM  AR6
  ;   POPM  AR1

     .if __far_mode
        fret
    .else
        ret
    .endif
      
;