can_bus.c

对于CAN总线应用于ATMEGA128的底层操作函数

1
4347A–CAN–06/04
CAN Program Examples
1. Introduction
This Application Note provides to customers C and Assembler program examples for
UART.
These examples are developped for the different configuration modes of this feature.
1.1 References Atmel 8051 Microcontrollers Hardware Manual. 8051
Microcontrollers
Application Note
2
4347A–CAN–06/04
2. C Example
2.1 Program
/**
* @file $RCSfile: can.c,v $
*
* Copyright (c) 2004 Atmel.
*
* Please read file license.txt for copyright notice.
*
* @brief This file is an example to use can networking.
*
* This file can be parsed by Doxygen for automatic documentation
* generation.
* Put here the functional description of this file within the software
* architecture of your program.
*
* @version $Revision: 1.0 $ $Name: $
*/
/* @section I N C L U D E S */
#include "t89c51cc01.h"
/* baud rate and bit timing parameters */
#define BRP_500k 0x00
#define SJW_500k 0x00
#define PRS_500k 0x02
#define PHS1_500k 0x03
#define PHS2_500k 0x03
unsigned char num_channel, num_data;
/**
* FUNCTION_PURPOSE: This file set up Can at 500Kbauds with channel 0 id 0x123
* in reception
* and channel 1 id 0x001 in emission.
* FUNCTION_INPUTS: void
* FUNCTION_OUTPUTS: void
*/
void main(void)
{
CANGCON |= MSK_CANGCON_GRES;/* reset CAN */
/* reset all mailboxes */
for (num_channel = 0; num_channel < 15; num_channel++)
{
CANPAGE = num_channel << 4;
CANCONCH = CH_DISABLE;
CANSTCH = 0;
CANIDT1 = 0;
CANIDT2 = 0;
3
4347A–CAN–06/04
CANIDT3 = 0;
CANIDT4 = 0;
CANIDM1 = 0;
CANIDM2 = 0;
CANIDM3 = 0;
CANIDM4 = 0;
for (num_data = 0; num_data < 8; num_data++) CANMSG = 0;
}
/* setup bit timing */
CANBT1 = BRP_500k << 1; /* BRP=0x00; */
CANBT2 &= ~0x60; /* reset SJW */
CANBT2 |= SJW_500k << 5; /* SJW=0x00; */
CANBT2 &= ~0x0E; /* reset PRS */
CANBT2 |= PRS_500k << 1; /* PRS=0x02; */
CANBT3 &= ~0x70; /* reset PHS2 */
CANBT3 |= PHS2_500k << 4; /* PHS2=0x03;*/
CANBT3 &= ~0x0E; /* reset PHS1 */
CANBT3 |= PHS1_500k << 1; /* PHS1=0x03 */
CANGCON |= MSK_CANGCON_ENA; /* start CAN */
/* Channel 0 init */
CANPAGE = (0 << 4); /* CHNB=0x00; select channel 0 */
CANSTCH = 0x00; /* reset channel staus */
CANCONCH = CH_DISABLE; /* reset control and dlc register */
/* Channel 0: identifier = 11bits. CANIDT=0x123 */
CANIDT1 = 0x24;
CANIDT2 &= ~0x80;
CANIDT2 |= 0x60;
/* Channel 0: mask = 11bits. 0x7F0 */
CANIDM1 = 0xFE;
CANIDM2 &= ~0xE0;
CANIDM4 = 0;
/* Channel 0 configuration */
CANIDT4 &=~0x04; /* clear bit rtr in CANIDT4. */
CANCONCH |= DLC_MAX; /* Reception 8 bytes.*/
CANCONCH |= CH_RxENA; /* Reception enabled without
buffer.*/
/* Channel 1 init */
CANPAGE = (1 << 4); /* CHNB=0x01; select channel 1 */
CANSTCH = 0x00; /* reset channel staus */
CANCONCH = CH_DISABLE; /* reset control and dlc register */
/* Channel 1: identifier = 11bits. CANIDT=0x001 */
CANIDT1 = 0x80;
CANIDT2 &= ~0xC0;
CANIDT2 |= 0x20;
4
4347A–CAN–06/04
/* interrupt configuration */
CANIE2|=0x01; /* IECH0=1 */
CANGIE |= MSK_CANGIE_ENTX; /* Can_Tx IT enable */
CANGIE |= MSK_CANGIE_ENRX; /* Can_Rx IT enable */
ECAN = 1; /* CAN IT enable */
EA = 1; /* all IT enable */
while(1); /* endless */
}
/**
* FUNCTION_PURPOSE: can interrupt. echo receive data on channel 0 reception.
* Reception id between 0x120 and 0x12F.
* FUNCTION_INPUTS: P4.1(RxDC) can input
* FUNCTION_OUTPUTS: P4.0(TxDC) can output
*/
can_it(void) interrupt 7
{
char save_canpage;
char i; /* can_data index */
char can_data[8];
save_canpage = CANPAGE; /* save current context */
/* echo receive data on channel 0 reception */
CANPAGE = (0 << 4); /* CHNB=0x00; select channel 0 */
if(CANSTCH==MSK_CANSTCH_RxOk)
{
for (i=0; i<8; i++) can_data[i] = CANMSG; /* save receive data */
CANPAGE = (1 << 4); /* CHNB=0x00; select channel 1 */
/* Channel 1 configuration */
CANCONCH = CH_DISABLE; /* reset channel 1 configuration
*/
for (i=0; i<8; i++) CANMSG = can_data[i]; /* load saved data */
CANCONCH |= DLC_MAX; /* transmit 8 bytes */
CANCONCH |= CH_TxENA; /* emission enabled */
CANEN2 |= (1 << 1); /* channel 1 enable */
CANSTCH=0x00; /* reset channel 1 status */
}
CANPAGE = (0 << 4); /* CHNB=0x00; select channel 0 */
CANCONCH = CH_DISABLE; /* reset channel 0 configuration */
CANCONCH |= DLC_MAX; /* receive 8 bytes */
CANCONCH |= CH_RxENA; /* reception enable */
CANEN2 |= (1 << 0); /* channel 0 enable */
CANSTCH=0x00; /* reset channel 0 status */
CANPAGE= save_canpage; /* restore saved context */
CANGIT = 0x00; /* reset all flags */
}
5
4347A–CAN–06/04
2.2 SFR Register Definition
/*H*************************************************************************
**
* NAME: T89C51CC01.h
*---------------------------------------------------------------------------
-
* PURPOSE: inlcude file for KEIL
****************************************************************************
*/
#ifndef _T89C51CC01_H_
#define _T89C51CC01_H_
#define Sfr(x, y) sfr x = y
#define Sbit(x, y, z) sbit x = y^z
#define Sfr16(x,y)sfr16 x = y
/*----------------------------------------*/
/* Include file for 8051 SFR Definitions */
/*----------------------------------------*/
/* BYTE Register */
Sfr (P0 , 0x80);
Sfr (P1 , 0x90);
Sbit (P1_7, 0x90, 7);
Sbit (P1_6, 0x90, 6);
Sbit (P1_5, 0x90, 5);
Sbit (P1_4, 0x90, 4);
Sbit (P1_3, 0x90, 3);
Sbit (P1_2, 0x90, 2);
Sbit (P1_1, 0x90, 1);
Sbit (P1_0, 0x90, 0);
Sfr (P2 , 0xA0);
Sbit (P2_7 , 0xA0, 7);
Sbit (P2_6 , 0xA0, 6);
Sbit (P2_5 , 0xA0, 5);
Sbit (P2_4 , 0xA0, 4);
Sbit (P2_3 , 0xA0, 3);
Sbit (P2_2 , 0xA0, 2);
Sbit (P2_1 , 0xA0, 1);
Sbit (P2_0 , 0xA0, 0);
Sfr (P3 , 0xB0);
Sbit (P3_7 , 0xB0, 7);
Sbit (P3_6 , 0xB0, 6);
6
4347A–CAN–06/04
Sbit (P3_5 , 0xB0, 5);
Sbit (P3_4 , 0xB0, 4);
Sbit (P3_3 , 0xB0, 3);
Sbit (P3_2 , 0xB0, 2);
Sbit (P3_1 , 0xB0, 1);
Sbit (P3_0 , 0xB0, 0);
Sbit (RD , 0xB0, 7);
Sbit (WR , 0xB0, 6);
Sbit (T1 , 0xB0, 5);
Sbit (T0 , 0xB0, 4);
Sbit (INT1, 0xB0, 3);
Sbit (INT0, 0xB0, 2);
Sbit (TXD , 0xB0, 1);
Sbit (RXD , 0xB0, 0);
Sfr (P4 , 0xC0);
Sfr (PSW , 0xD0);
Sbit (CY , 0xD0, 7);
Sbit (AC , 0xD0, 6);
Sbit (F0 , 0xD0, 5);
Sbit (RS1 , 0xD0, 4);
Sbit (RS0 , 0xD0, 3);
Sbit (OV , 0xD0, 2);
Sbit (UD , 0xD0, 1);
Sbit (P , 0xD0, 0);
Sfr (ACC , 0xE0);
Sfr (B , 0xF0);
Sfr (SP , 0x81);
Sfr (DPL , 0x82);
Sfr (DPH , 0x83);
Sfr (PCON , 0x87);
Sfr (CKCON , 0x8F);
/*------------------ TIMERS registers ---------------------*/
Sfr (TCON , 0x88);
Sbit (TF1 , 0x88, 7);
Sbit (TR1 , 0x88, 6);
Sbit (TF0 , 0x88, 5);
Sbit (TR0 , 0x88, 4);
Sbit (IE1 , 0x88, 3);
Sbit (IT1 , 0x88, 2);
Sbit (IE0 , 0x88, 1);
Sbit (IT0 , 0x88, 0);
Sfr (TMOD , 0x89);
7
4347A–CAN–06/04
Sfr (T2CON , 0xC8);
Sbit (TF2 , 0xC8, 7);
Sbit (EXF2 , 0xC8, 6);
Sbit (RCLK , 0xC8, 5);
Sbit (TCLK , 0xC8, 4);
Sbit (EXEN2 , 0xC8, 3);
Sbit (TR2 , 0xC8, 2);
Sbit (C_T2 , 0xC8, 1);
Sbit (CP_RL2, 0xC8, 0);
Sfr (T2MOD , 0xC9);
Sfr (TL0 , 0x8A);
Sfr (TL1 , 0x8B);
Sfr (TL2 , 0xCC);
Sfr (TH0 , 0x8C);
Sfr (TH1 , 0x8D);
Sfr (TH2 , 0xCD);
Sfr (RCAP2L , 0xCA);
Sfr (RCAP2H , 0xCB);
Sfr (WDTRST , 0xA6);
Sfr (WDTPRG , 0xA7);
/*------------------- UART registers ------------------------*/
Sfr (SCON , 0x98);
Sbit (SM0 , 0x98, 7);
Sbit (FE , 0x98, 7);
Sbit (SM1 , 0x98, 6);
Sbit (SM2 , 0x98, 5);
Sbit (REN , 0x98, 4);
Sbit (TB8 , 0x98, 3);
Sbit (RB8 , 0x98, 2);
Sbit (TI , 0x98, 1);
Sbit (RI , 0x98, 0);
Sfr (SBUF , 0x99);
Sfr (SADEN , 0xB9);
Sfr (SADDR , 0xA9);
/*-------------------- ADC registers ----------------------*/
Sfr (ADCLK , 0xF2);
Sfr (ADCON , 0xF3);
#define MSK_ADCON_PSIDLE 0x40
#define MSK_ADCON_ADEN 0x20
#define MSK_ADCON_ADEOC 0x10
#define MSK_ADCON_ADSST 0x08
#define MSK_ADCON_SCH 0x07
Sfr (ADDL , 0xF4);
#define MSK_ADDL_UTILS 0x03
8
4347A–CAN–06/04
Sfr (ADDH , 0xF5);
Sfr (ADCF , 0xF6);
/*-------------------- FLASH EEPROM registers ------------*/
Sfr (FCON , 0xD1);
#define MSK_FCON_FBUSY 0x01
#define MSK_FCON_FMOD 0x06
#define MSK_FCON_FPS 0x08
#define MSK_FCON_FPL 0xF0
Sfr (EECON , 0xD2);
#define MSK_EECON_EEBUSY 0x01
#define MSK_EECON_EEE 0x02
#define MSK_EECON_EEPL 0xF0
Sfr (AUXR , 0x8E);
#define MSK_AUXR_M0 0x20
Sfr (AUXR1 , 0xA2);
#define MSK_AUXR1_ENBOOT 0x20
/*-------------------- IT registers -----------------------*/
Sfr (IPL1 , 0xF8);
Sfr (IPH1 , 0xF7);
Sfr (IEN0 , 0xA8);
Sfr (IPL0 , 0xB8);
Sfr (IPH0 , 0xB7);
Sfr (IEN1 , 0xE8);
/* IEN0 */
Sbit (EA , 0xA8, 7);
Sbit (EC , 0xA8, 6);
Sbit (ET2 , 0xA8, 5);
Sbit (ES , 0xA8, 4);
Sbit (ET1 , 0xA8, 3);
Sbit (EX1 , 0xA8, 2);
Sbit (ET0 , 0xA8, 1);
Sbit (EX0 , 0xA8, 0);
/* IEN1 */
Sbit (ETIM , 0xE8, 2);
Sbit (EADC , 0xE8, 1);
Sbit (ECAN , 0xE8, 0);
/*--------------------- PCA registers --------------------*/
Sfr (CCON , 0xD8);
Sbit(CF , 0xD8, 7);
Sbit(CR , 0xD8, 6);
Sbit(CCF4, 0xD8, 4);
Sbit(CCF3, 0xD8, 3);
Sbit(CCF2, 0xD8, 2);
Sbit(CCF1, 0xD8, 1);
Sbit(CCF0, 0xD8, 0);
9
4347A–CAN–06/04
Sfr (CMOD , 0xD9);
Sfr (CH , 0xF9);
Sfr (CL , 0xE9);
Sfr (CCAP0H , 0xFA);
Sfr (CCAP0L , 0xEA);
Sfr (CCAPM0 , 0xDA);
Sfr (CCAP1H , 0xFB);
Sfr (CCAP1L , 0xEB);
Sfr (CCAPM1 , 0xDB);
Sfr (CCAP2H , 0xFC);
Sfr (CCAP2L , 0xEC);
Sfr (CCAPM2 , 0xDC);
Sfr (CCAP3H , 0xFD);
Sfr (CCAP3L , 0xED);
Sfr (CCAPM3 , 0xDD);
Sfr (CCAP4H , 0xFE);
Sfr (CCAP4L , 0xEE);
Sfr (CCAPM4 , 0xDE);
/*------------------- CAN registers --------------------------*/
Sfr (CANGIT , 0x9B);
#define MSK_CANGIT_CANIT0x80
#define MSK_CANGIT_OVRTIM 0x20
#define MSK_CANGIT_OVRBUF0x10
#define MSK_CANGIT_SERG0x08
#define MSK_CANGIT_CERG0x04
#define MSK_CANGIT_FERG0x02
#define MSK_CANGIT_AERG0x01
Sfr (CANTEC , 0x9C);
Sfr (CANREC , 0x9D);
Sfr (CANTCON , 0xA1);
Sfr (CANMSG , 0xA3);
Sfr (CANTTCL , 0xA4);
Sfr (CANTTCH , 0xA5);
Sfr (CANGSTA , 0xAA);
#define MSK_CANGSTA_OVFG0x40
#define MSK_CANGSTA_TBSY0x10
#define MSK_CANGSTA_RBSY0x08
#define MSK_CANGSTA_ENFG0x04
#define MSK_CANGSTA_BOFF0x02
#define MSK_CANGSTA_ERRP0x01
Sfr (CANGCON , 0xAB);
#define MSK_CANGCON_ABRQ 0x80
#define MSK_CANGCON_OVRQ 0x40
#define MSK_CANGCON_TTC 0x20
#define MSK_CANGCON_SYNCTTC 0x10
#define TTC_EOF 0x10
#define TTC_SOF 0x00
10
4347A–CAN–06/04
#define MSK_CANGCON_AUTBAUD 0x08
#define MSK_CANGCON_ENA 0x02
#define MSK_CANGCON_GRES 0x01
Sfr (CANTIML , 0xAC);
Sfr (CANTIMH , 0xAD);
Sfr (CANSTMPL , 0xAE);
Sfr (CANSTMPH , 0xAF);
Sfr (CANPAGE , 0xB1);
Sfr (CANSTCH , 0xB2);
#define MSK_CANSTCH_DLCW 0x80
#define MSK_CANSTCH_TxOk 0x40
#define MSK_CANSTCH_RxOk 0x20
#define MSK_CANSTCH_BERR 0x10
#define MSK_CANSTCH_SERR 0x08
#define MSK_CANSTCH_CERR 0x04
#define MSK_CANSTCH_FERR 0x02
#define MSK_CANSTCH_AERR 0x01
Sfr (CANCONCH , 0xB3);
#define MSK_CANCONCH_IDE 0x10
#define MSK_CANCONCH_DLC 0x0F
#define MSK_CANCONCH_CONF 0xC0
#define DLC_MAX 8
#define CH_DISABLE 0x00
#define CH_RxENA 0x80
#define CH_TxENA 0x40
#define CH_RxBENA 0xC0
Sfr (CANBT1 , 0xB4);
#define CAN_PRESCALER_MIN 0
#define CAN_PRESCALER_MAX 63
Sfr (CANBT2 , 0xB5);
#define MSK_CANBT2_SJW 0x60
#define MSK_CANBT2_PRS 0x0E
#define CAN_SJW_MIN 0
#define CAN_SJW_MAX 3
#define CAN_PRS_MIN 0
#define CAN_PRS_MAX 7
Sfr (CANBT3 , 0xB6);
#define MSK_CANBT3_PHS2 0x70
#define MSK_CANBT3_PHS1 0x0E
#define CAN_PHS2_MIN 0
#define CAN_PHS2_MAX 7
#define CAN_PHS1_MIN 0
#define CAN_PHS1_MAX 7
11
4347A–CAN–06/04
Sfr (CANSIT1 , 0xBA);
Sfr (CANSIT2 , 0xBB);
Sfr (CANIDT1 , 0xBC);
Sfr (CANIDT2 , 0xBD);
Sfr (CANIDT3 , 0xBE);
Sfr (CANIDT4 , 0xBF);
#define MSK_CANIDT4_RTRTAG 0x04
Sfr (CANGIE , 0xC1);
#define MSK_CANGIE_ENRX 0x20
#define MSK_CANGIE_ENTX 0x10
#define MSK_CANGIE_ENERCH 0x08
#define MSK_CANGIE_ENBUF 0x04
#define MSK_CANGIE_ENERG 0x02
Sfr (CANIE1 , 0xC2);
Sfr (CANIE2 , 0xC3);
Sfr (CANIDM1 , 0xC4);
Sfr (CANIDM2 , 0xC5);
Sfr (CANIDM3 , 0xC6);
Sfr (CANIDM4 , 0xC7);
#define MSK_CANIDM4_RTRMSK 0x04
#define MSK_CANIDM4_IDEMSK 0x01
Sfr (CANEN1 , 0xCE);
Sfr (CANEN2 , 0xCF);
#endif
12
4347A–CAN–06/04
3. Assembly 51 Examples
3.1 Program
$INCLUDE (t89c51cc01.INC)
num_channel DATA 10H
num_data DATA 11H
data0 DATA 12H
data1 DATA 13H
data2 DATA 14H
data3 DATA 15H
data4 DATA 16H