📄 lpc21xx.inc
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;/*************************************************************************/
;/* */
;/* FILE NAME VERSION */
;/* */
;/* ARM2132 Board version 1.0 */
;/* */
;/* COMPONENT */
;/* */
;/* DESCRIPTION */
;/* */
;/* ARM7TDMI for LPC2132 ASSEBLER SYSTEM HEADER FILE */
;/* */
;/* AUTHOR */
;/* */
;/* Dr WangZhenXing ,TsingHua University */
;/* 2005-4-18 www.wL88.net */
;/*************************************************************************/
;/* Format of the Program Status Register */
;/*************************************************************************/
;/* */
;/* 31 30 29 28 7 6 5 4 3 2 1 0 */
;/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+ */
;/*| N | Z | C | V | | I | F | T | M4 ~ M0 | */
;/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+ */
;/* */
;/* Processor Mode and Mask */
;/* */
;/*************************************************************************/
;
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F ; available on ARM Arch 4 and later
MASK_MODE EQU 0x0000003F
MODE_SVC32 EQU 0x00000013
I_BIT EQU 0x80 ; when I bit is set, IRQ is disabled
F_BIT EQU 0x40 ; when F bit is set, FIQ is disabled
; --- System memory locations
MEMMAP EQU 0xE01FC0C4 ; Address of MEMMAP
Remap_Ram EQU 0x04 ; remap for ram execution
Remap_Boot EQU 0x00 ;remap for boot blocks
; --- Amount of memory (in bytes) allocated for stacks
Len_FIQ_Stack EQU 40
Len_IRQ_Stack EQU 40
Len_ABT_Stack EQU 0
Len_UND_Stack EQU 0
Len_SVC_Stack EQU 40
Len_USR_Stack EQU 0
Len_SYS_Stack EQU 0
; Add lengths >0 for FIQ_Stack, ABT_Stack, UND_Stack if you need them.
; Offsets will be loaded as immediate values.
; Offsets must be 8 byte aligned.
Offset_FIQ_Stack EQU 0
Offset_IRQ_Stack EQU Offset_FIQ_Stack + Len_FIQ_Stack
Offset_ABT_Stack EQU Offset_IRQ_Stack + Len_IRQ_Stack
Offset_UND_Stack EQU Offset_ABT_Stack + Len_ABT_Stack
Offset_SVC_Stack EQU Offset_UND_Stack + Len_UND_Stack
Offset_USR_Stack EQU Offset_SVC_Stack + Len_SVC_Stack
Offset_SYS_Stack EQU Offset_USR_Stack + Len_USR_Stack
;/*************************************************************************/
;/* SYSTEM STACK MEMORY : 8K bytes system stacks are defined at memory.a
;/*************************************************************************/
;USR_STACK_SIZE EQU 1024
;UDF_STACK_SIZE EQU 0
;ABT_STACK_SIZE EQU 0
;IRQ_STACK_SIZE EQU 1024
;FIQ_STACK_SIZE EQU 1024
;SUP_STACK_SIZE EQU 2048
;/*************************************************************************/
;/* SYSTEM USER STACK MEMORY
;/*************************************************************************/
;SYSTEM_SIZE EQU 2048 ; Define the system stack size
;TIMER_SIZE EQU 1024 ; Define timer HISR stack size
;TIMER_PRIORITY EQU 2 ; Timer HISR priority (values from
; ; 0 to 2, where 0 is highest)
;/* EXTERNAL MEMORY CONTROLLER (EMC) */
;/* 外部总线控制器 */
;this section is used for philips lpc21xx
BCFG0 EQU 0xFFE00000 ;/* lpc22xx only */
BCFG1 EQU 0xFFE00004 ;/* lpc22xx only */
BCFG2 EQU 0xFFE00008 ;/* lpc22xx only */
BCFG3 EQU 0xFFE0000C ;/* lpc22xx only */
;/* External Interrupts */
;/* 外部中断控制寄存器 */
EXTINT EQU 0xE01FC140
EXTWAKE EQU 0xE01FC144
EXTMODE EQU 0xE01FC148 ;/* no in lpc210x*/
EXTPOLAR EQU 0xE01FC14C ;/* no in lpc210x*/
;/* Phase Locked Loop (PLL) */
;/* PLL控制寄存器 */
PLLCON EQU 0xE01FC080
PLLCFG EQU 0xE01FC084
PLLSTAT EQU 0xE01FC088
PLLFEED EQU 0xE01FC08C
;/* Power Control */
;/* 功率控制寄存器 */
PCON EQU 0xE01FC0C0
PCONP EQU 0xE01FC0C4
;/* VPB Divider */
;/* VLSI外设总线（VPB）分频寄存器 */
VPBDIV EQU 0xE01FC100
;/* Memory Accelerator Module (MAM) */
;/* 存储器加速模块 */
MAMCR EQU 0xE01FC000
MAMTIM EQU 0xE01FC004
;/* Vectored Interrupt Controller (VIC) */
;/* 向量中断控制器(VIC)的特殊寄存器 */
VICIRQStatus EQU 0xFFFFF000
VICFIQStatus EQU 0xFFFFF004
VICRawIntr EQU 0xFFFFF008
VICIntSelect EQU 0xFFFFF00C
VICIntEnable EQU 0xFFFFF010
VICIntEnClr EQU 0xFFFFF014
VICSoftInt EQU 0xFFFFF018
VICSoftIntClear EQU 0xFFFFF01C
VICProtection EQU 0xFFFFF020
VICVectAddr EQU 0xFFFFF030
VICDefVectAddr EQU 0xFFFFF034
VICVectAddr0 EQU 0xFFFFF100
VICVectAddr1 EQU 0xFFFFF104
VICVectAddr2 EQU 0xFFFFF108
VICVectAddr3 EQU 0xFFFFF10C
VICVectAddr4 EQU 0xFFFFF110
VICVectAddr5 EQU 0xFFFFF114
VICVectAddr6 EQU 0xFFFFF118
VICVectAddr7 EQU 0xFFFFF11C
VICVectAddr8 EQU 0xFFFFF120
VICVectAddr9 EQU 0xFFFFF124
VICVectAddr10 EQU 0xFFFFF128
VICVectAddr11 EQU 0xFFFFF12C
VICVectAddr12 EQU 0xFFFFF130
VICVectAddr13 EQU 0xFFFFF134
VICVectAddr14 EQU 0xFFFFF138
VICVectAddr15 EQU 0xFFFFF13C
VICVectCntl0 EQU 0xFFFFF200
VICVectCntl1 EQU 0xFFFFF204
VICVectCntl2 EQU 0xFFFFF208
VICVectCntl3 EQU 0xFFFFF20C
VICVectCntl4 EQU 0xFFFFF210
VICVectCntl5 EQU 0xFFFFF214
VICVectCntl6 EQU 0xFFFFF218
VICVectCntl7 EQU 0xFFFFF21C
VICVectCntl8 EQU 0xFFFFF220
VICVectCntl9 EQU 0xFFFFF224
VICVectCntl10 EQU 0xFFFFF228
VICVectCntl11 EQU 0xFFFFF22C
VICVectCntl12 EQU 0xFFFFF230
VICVectCntl13 EQU 0xFFFFF234
VICVectCntl14 EQU 0xFFFFF238
VICVectCntl15 EQU 0xFFFFF23C
;/* Pin Connect Block */
;/* 管脚连接模块控制寄存器 */
PINSEL0 EQU 0xE002C000
PINSEL1 EQU 0xE002C004
PINSEL2 EQU 0xE002C014 ;/* no in lpc210x*/
;/* General Purpose Input/Output (GPIO) */
;/* 通用并行IO口的特殊寄存器 */
IOPIN EQU 0xE0028000 ;/* lpc210x only */
IOSET EQU 0xE0028004 ;/* lpc210x only */
IODIR EQU 0xE0028008 ;/* lpc210x only */
IOCLR EQU 0xE002800C ;/* lpc210x only */
IO0PIN EQU 0xE0028000 ;/* no in lpc210x*/
IO0SET EQU 0xE0028004 ;/* no in lpc210x*/
IO0DIR EQU 0xE0028008 ;/* no in lpc210x*/
IO0CLR EQU 0xE002800C ;/* no in lpc210x*/
IO1PIN EQU 0xE0028010 ;/* no in lpc210x*/
IO1SET EQU 0xE0028014 ;/* no in lpc210x*/
IO1DIR EQU 0xE0028018 ;/* no in lpc210x*/
IO1CLR EQU 0xE002801C ;/* no in lpc210x*/
IO2PIN EQU 0xE0028020 ;/* lpc22xx only */
IO2SET EQU 0xE0028024 ;/* lpc22xx only */
IO2DIR EQU 0xE0028028 ;/* lpc22xx only */
IO2CLR EQU 0xE002802C ;/* lpc22xx only */
IO3PIN EQU 0xE0028030 ;/* lpc22xx only */
IO3SET EQU 0xE0028034 ;/* lpc22xx only */
IO3DIR EQU 0xE0028038 ;/* lpc22xx only */
IO3CLR EQU 0xE002803C ;/* lpc22xx only */
;/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
;/* 通用异步串行口0(UART0)的特殊寄存器 */
U0RBR EQU 0xE000C000
U0THR EQU 0xE000C000
U0IER EQU 0xE000C004
U0IIR EQU 0xE000C008
U0FCR EQU 0xE000C008
U0LCR EQU 0xE000C00C
U0LSR EQU 0xE000C014
U0SCR EQU 0xE000C01C
U0DLL EQU 0xE000C000
U0DLM EQU 0xE000C004
;/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
;/* 通用异步串行口1(UART1)的特殊寄存器 */
U1RBR EQU 0xE0010000
U1THR EQU 0xE0010000
U1IER EQU 0xE0010004
U1IIR EQU 0xE0010008
U1FCR EQU 0xE0010008
U1LCR EQU 0xE001000C
U1MCR EQU 0xE0010010
U1LSR EQU 0xE0010014
U1MSR EQU 0xE0010018
U1SCR EQU 0xE001001C
U1DLL EQU 0xE0010000
U1DLM EQU 0xE0010004
;/* I2C (8/16 bit data bus) */
;/* 芯片间总线（I2C）的特殊寄存器 */
I2CONSET EQU 0xE001C000
I2STAT EQU 0xE001C004
I2DAT EQU 0xE001C008
I2ADR EQU 0xE001C00C
I2SCLH EQU 0xE001C010
I2SCLL EQU 0xE001C014
I2CONCLR EQU 0xE001C018
;/* SPI (Serial Peripheral Interface) */
;/* SPI总线接口的特殊寄存器 */
; /* only for lpc210x*/
SPI_SPCR EQU 0xE0020000
SPI_SPSR EQU 0xE0020004
SPI_SPDR EQU 0xE0020008
SPI_SPCCR EQU 0xE002000C
SPI_SPINT EQU 0xE002001C
S0PCR EQU 0xE0020000 ;/* no in lpc210x*/
S0PSR EQU 0xE0020004 ;/* no in lpc210x*/
S0PDR EQU 0xE0020008 ;/* no in lpc210x*/
S0PCCR EQU 0xE002000C ;/* no in lpc210x*/
S0PINT EQU 0xE002001C ;/* no in lpc210x*/
S1PCR EQU 0xE0030000 ;/* no in lpc210x*/
S1PSR EQU 0xE0030004 ;/* no in lpc210x*/
S1PDR EQU 0xE0030008 ;/* no in lpc210x*/
S1PCCR EQU 0xE003000C ;/* no in lpc210x*/
S1PINT EQU 0xE003001C ;/* no in lpc210x*/
;/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
;/* CAN控制器和接收路波器 */
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