📄 usb_9602.lst
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34 =1 /*Descriptor Types*/
35 =1 #define DEVICE 0x01
36 =1 #define CONFIGURATION 0x02
37 =1 #define XSTRING 0x03
38 =1 #define INTERFACE 0x04
39 =1 #define ENDPOINT 0x05
40 =1 #define HID 0x21
41 =1 #define HIDREPORT 0x22
42 =1 #define HIDPHYSICAL 0x23
43 =1
44 =1 /*Lengths of various descriptor segments*/
45 =1 #define DEV_LENGTH 18 /*length of device desc. */
46 =1 #define CFG_LENGTH 9 /*length of cfg. desc. seg*/
47 =1 #define INT_LENGTH 9 /*length of int. desc. seg*/
48 =1 #define HID_LENGTH 9 /*length of HID desc. seg*/
49 =1 #define END_LENGTH 7 /*length of end. desc. seg*/
50 =1
51 =1 /*Class codes*/
52 =1 #define HIDCLASS 0x03
53 =1 #define NOSUBCLASS 0x00
54 =1 #define BOOTSUBCLASS 0x01
55 =1 #define VENDORSPEC 0xFF
56 =1
57 =1 /*Recipient Selectors/Masks*/
58 =1 #define RECIPIENT_MASK 0x1F
59 =1 #define DEVICE_RECIPIENT 0x00
60 =1 #define INTERFACE_RECIPIENT 0x01
61 =1 #define ENDPOINT_RECIPIENT 0x02
62 =1 #define OTHER_RECIPIENT 0x03
63 =1
64 =1
65 =1 /*Feature Selectors*/
66 =1 #define DEVICE_REMOTE_WAKEUP 0x01
67 =1 #define ENDPOINT_STALL 0x00
68 =1
17 #include "def9602.h" /*include 9602 defines */
1 =1 /**********************************************************************/
2 =1 /* 9602 register and bit definitions */
3 =1 /**********************************************************************/
4 =1 #define MCNTRL 0x00 /*Main control register */
C51 COMPILER V5.50, USB_9602 02/12/99 16:05:13 PAGE 5
5 =1 #define CCONF 0x01 /*Clk. config. register */
6 =1 #define TCR 0x02 /*Xcvr config. register */
7 =1 #define RID 0x03 /*Rev. ID register */
8 =1 #define FAR 0x04 /*Func address register */
9 =1 #define NFSR 0x05 /*Node func st register */
10 =1 #define MAEV 0x06 /*Main event register */
11 =1 #define MAMSK 0x07 /*Main mask register */
12 =1 #define ALTEV 0x08 /*Alt. event register */
13 =1 #define ALTMSK 0x09 /*ALT mask register */
14 =1 #define TXEV 0x0A /*TX event register */
15 =1 #define TXMSK 0x0B /*TX mask register */
16 =1 #define RXEV 0x0C /*RX event register */
17 =1 #define RXMSK 0x0D /*RX mask register */
18 =1 #define NAKEV 0x0E /*NAK event register */
19 =1 #define NAKMSK 0x0F /*NAK mask register */
20 =1 #define FWEV 0x10 /*FIFO warning register */
21 =1 #define FWMSK 0x11 /*FIFO warning mask */
22 =1 #define FNH 0x12 /*Frame nbr hi register */
23 =1 #define FNL 0x13 /*Frame nbr lo register */
24 =1 #define DMACNTRL 0x14 /*DMA control register */
25 =1
26 =1 #define EPC0 0x20 /*Endpoint0 register */
27 =1 #define TXD0 0x21 /*TX data register 0 */
28 =1 #define TXS0 0x22 /*TX status register 0 */
29 =1 #define TXC0 0x23 /*TX command register 0 */
30 =1
31 =1 #define RXD0 0x25 /*RX data register 0 */
32 =1 #define RXS0 0x26 /*RX status register 0 */
33 =1 #define RXC0 0x27 /*RX command register 0 */
34 =1
35 =1 #define EPC1 0x28 /*Endpoint1 register */
36 =1 #define TXD1 0x29 /*TX data register 1 */
37 =1 #define TXS1 0x2A /*TX status register 1 */
38 =1 #define TXC1 0x2B /*TX command register 1 */
39 =1
40 =1 #define EPC2 0x2C /*Endpoint2 register */
41 =1 #define RXD1 0x2D /*RX data register 1 */
42 =1 #define RXS1 0x2E /*RX status register 1 */
43 =1 #define RXC1 0x2F /*RX command register 1 */
44 =1
45 =1 #define EPC3 0x30 /*Endpoint3 register */
46 =1 #define TXD2 0x31 /*TX data register 2 */
47 =1 #define TXS2 0x32 /*TX status register 2 */
48 =1 #define TXC2 0x33 /*TX command register 2 */
49 =1
50 =1 #define EPC4 0x34 /*Endpoint4 register */
51 =1 #define RXD2 0x35 /*RX data register 2 */
52 =1 #define RXS2 0x36 /*RX status register 2 */
53 =1 #define RXC2 0x37 /*RX command register 2 */
54 =1
55 =1 #define EPC5 0x38 /*Endpoint5 register */
56 =1 #define TXD3 0x39 /*TX data register 3 */
57 =1 #define TXS3 0x3A /*TX status register 3 */
58 =1 #define TXC3 0x3B /*TX command register 3 */
59 =1
60 =1 #define EPC6 0x3C /*Endpoint6 register */
61 =1 #define RXD3 0x3D /*RX data register 3 */
62 =1 #define RXS3 0x3E /*RX status register 3 */
63 =1 #define RXC3 0x3F /*RX command register 3 */
64 =1
65 =1 /* MCNTRL bits ********************************************************/
66 =1 #define SRST 0x01 /*software reset */
67 =1 #define DBG 0x02 /*debug mode */
68 =1 #define VGE 0x04 /*voltage regulator enable*/
69 =1 #define NAT 0x08 /*node attached */
70 =1 #define INT_DIS 0x00 /*interrupts disabled */
C51 COMPILER V5.50, USB_9602 02/12/99 16:05:13 PAGE 6
71 =1 #define INT_L_O 0x40 /*act lo ints, open drain */
72 =1 #define INT_H_P 0x80 /*act hi ints, push pull */
73 =1 #define INT_L_P 0xC0 /*act lo ints, push pull */
74 =1
75 =1 /* CCONF bits ********************************************************/
76 =1 #define CODIS 0x80 /*disable clock output */
77 =1
78 =1 /* FAR bits ********************************************************/
79 =1 #define AD_EN 0x80 /*address enable */
80 =1
81 =1 /* EPCX bits ********************************************************/
82 =1 #define DEF 0x40 /*force def. adr (0 only) */
83 =1 #define STALL 0x80 /*force stall handshakes */
84 =1 #define ISO 0x20 /*set for isochr. (1-3) */
85 =1 #define EP_EN 0x10 /*enables endpt. (1-3) */
86 =1
87 =1 /* NFSR bits ********************************************************/
88 =1 #define RST_ST 0x00 /*reset state */
89 =1 #define RSM_ST 0x01 /*resume state */
90 =1 #define OPR_ST 0x02 /*operational state */
91 =1 #define SUS_ST 0x03 /*suspend state */
92 =1
93 =1 /* MAEV, MAMSK bits ***************************************************/
94 =1 #define WARN 0x01 /*warning bit has been set*/
95 =1 #define ALT 0x02 /*alternate event */
96 =1 #define TX_EV 0x04 /*transmit event */
97 =1 #define FRAME 0x08 /*SOF packet received */
98 =1 #define NAK 0x10 /*NAK event */
99 =1 #define ULD 0x20 /*unlock locked detected */
100 =1 #define RX_EV 0x40 /*receive event */
101 =1 #define INTR_E 0x80 /*master interrupt enable */
102 =1
103 =1 /* ALTEV, ALTMSK bits *************************************************/
104 =1 #define EOP 0x08 /*end of packet */
105 =1 #define SD3 0x10 /*3 ms suspend */
106 =1 #define SD5 0x20 /*5 ms suspend */
107 =1 #define RESET_A 0x40 /*reset detected */
108 =1 #define RESUME_A 0x80 /*resume detected */
109 =1
110 =1 /* TXEV, TXMSK bits ***************************************************/
111 =1 #define TXFIFO0 0x01 /*TX_DONE, FIFO 0 */
112 =1 #define TXFIFO1 0x02 /*TX_DONE, FIFO 1 */
113 =1 #define TXFIFO2 0x04 /*TX_DONE, FIFO 2 */
114 =1 #define TXFIFO3 0x08 /*TX_DONE, FIFO 3 */
115 =1 #define TXUDRN0 0x10 /*TX_URUN, FIFO 0 */
116 =1 #define TXUDRN1 0x20 /*TX_URUN, FIFO 1 */
117 =1 #define TXUDRN2 0x40 /*TX_URUN, FIFO 2 */
118 =1 #define TXUDRN3 0x80 /*TX_URUN, FIFO 3 */
119 =1
120 =1 /* RXEV, RXMSK bits ***************************************************/
121 =1 #define RXFIFO0 0x01 /*RX_DONE, FIFO 0 */
122 =1 #define RXFIFO1 0x02 /*RX_DONE, FIFO 1 */
123 =1 #define RXFIFO2 0x04 /*RX_DONE, FIFO 2 */
124 =1 #define RXFIFO3 0x08 /*RX_DONE, FIFO 3 */
125 =1 #define RXOVRN0 0x10 /*RX_OVRN, FIFO 0 */
126 =1 #define RXOVRN1 0x20 /*RX_OVRN, FIFO 1 */
127 =1 #define RXOVRN2 0x40 /*RX_OVRN, FIFO 2 */
128 =1 #define RXOVRN3 0x80 /*RX_OVRN, FIFO 3 */
129 =1
130 =1 /* NAKEV, NAKMSK bits *************************************************/
131 =1 #define NAK_I0 0x01 /*IN NAK, FIFO 0 */
132 =1 #define NAK_I1 0x02 /*IN NAK, FIFO 1 */
133 =1 #define NAK_I2 0x04 /*IN NAK, FIFO 2 */
134 =1 #define NAK_I3 0x08 /*IN NAK, FIFO 3 */
135 =1 #define NAK_O0 0x10 /*OUT NAK, FIFO 0 */
136 =1 #define NAK_O1 0x20 /*OUT NAK, FIFO 1 */
C51 COMPILER V5.50, USB_9602 02/12/99 16:05:13 PAGE 7
137 =1 #define NAK_O2 0x40 /*OUT NAK, FIFO 2 */
138 =1 #define NAK_O3 0x80 /*OUT NAK, FIFO 3 */
139 =1
140 =1 /* TXCx bits ********************************************************/
141 =1 #define TX_EN 0x01 /*transmit enable */
142 =1 #define TX_LAST 0x02 /*last data in FIFO */
143 =1 #define TX_TOGL 0x04 /*specifies PID used */
144 =1 #define FLUSH 0x08 /*flushes all FIFO data */
145 =1 #define IGN_IN 0x10 /*ignore in tokens */
146 =1
147 =1 /* TXS0 bits ********************************************************/
148 =1 #define TX_DONE 0x20 /*transmit done */
149 =1 #define ACK_STAT 0x40 /*ack status of xmission */
150 =1
151 =1 /* RXC0 bits ********************************************************/
152 =1 #define RX_EN 0x01 /*receive enable */
153 =1 #define IGN_OUT 0x02 /*ignore out tokens */
154 =1 #define IGN_SETUP 0x04 /*ignore setup tokens */
155 =1
156 =1 /* RXS0 bits ********************************************************/
157 =1 #define RX_LAST 0x10 /*indicates RCOUNT valid */
158 =1 #define RX_TOGL 0x20 /*last pkt was DATA1 PID */
159 =1 #define SETUP_R 0x40 /*setup packet received */
160 =1 #define RX_ERR 0x80 /*last packet had an error*/
161 =1
162 =1 /**********************************************************************/
163 =1 /* 9602 commands and constants */
164 =1 /**********************************************************************/
165 =1 #define USBREAD 0x00 /*reads data at spec. addr*/
166 =1 #define USBWRITE 0x80 /*write selected register */
167 =1 #define USBBURST 0xC0 /*burst write */
168 =1
169 =1
18 #include "bitops.h"
1 =1 /*These are the standard ANSI bit operation macros. They are used by */
2 =1 /*microcontrollers that don't have special bit operation instructions.*/
3 =1
4 =1 #define BIT(x) (1 << (x)) /*used by bit op macros */
5 =1
6 =1 #define BIT0 0x01 /*used by bit op macros */
7 =1 #define BIT1 0x02
8 =1 #define BIT2 0x04
9 =1 #define BIT3 0x08
10 =1 #define BIT4 0x10
11 =1 #define BIT5 0x20
12 =1 #define BIT6 0x40
13 =1 #define BIT7 0x80
14 =1
15 =1 /* this macro sets a bit in the specified register or memory location */
16 =1 #define SETBIT(reg,bit) reg|=bit
17 =1
18 =1 /* this macro clrs a bit in the specified register or memory location */
19 =1 #define CLRBIT(reg,bit) reg&=(~bit)
20 =1
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