test.map.rpt

altera公司的FPGA的一些开发用的VHDL的源代码用于学习

Info: Elaborating entity "lpm_bustri" for hierarchy "bt:inst4|lpm_bustri:lpm_bustri_component"
Warning: Reduced register "int:inst10|la[31]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "int:inst10|la[30]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "int:inst10|la[29]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "int:inst10|la[28]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "int:inst10|la[27]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "int:inst10|la[26]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "int:inst10|la[25]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "int:inst10|la[24]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "int:inst10|la[23]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "int:inst10|la[22]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "int:inst10|la[21]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "int:inst10|la[20]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "int:inst10|la[19]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "int:inst10|la[18]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "int:inst10|la[17]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "int:inst10|la[16]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "int:inst10|la[15]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "int:inst10|la[14]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "int:inst10|la[13]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "int:inst10|la[12]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "int:inst10|la[11]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "int:inst10|la[10]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "int:inst10|la[9]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "int:inst10|la[8]~reg0" with stuck data_in port to stuck value GND
Info: Power-up level of register "int:inst10|la[7]~reg0" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "int:inst10|la[7]~reg0" with stuck data_in port to stuck value VCC
Info: Power-up level of register "int:inst10|la[6]~reg0" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "int:inst10|la[6]~reg0" with stuck data_in port to stuck value VCC
Warning: Reduced register "int:inst10|la[4]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "int:inst10|la[2]~reg0" with stuck data_in port to stuck value GND
Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[31]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[30]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[29]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[28]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[27]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[26]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[25]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[24]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[23]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[22]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[21]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[20]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[19]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[18]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[17]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[16]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[15]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[14]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[13]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[12]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[11]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[10]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[9]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[8]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[7]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[6]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[5]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[4]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[3]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[2]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[1]" that feeds logic to a wire
    Warning: Converting TRI node "bt:inst4|lpm_bustri:lpm_bustri_component|din[0]" that feeds logic to a wire
Info: Duplicate registers merged to single register
    Info: Duplicate register "int:inst10|ads~reg0" merged to single register "int:inst10|ccs~reg0"
    Info: Duplicate register "int:inst10|la[5]~reg0" merged to single register "int:inst10|wr~reg0"
    Info: Duplicate register "int:inst10|la[3]~reg0" merged to single register "int:inst10|wr~reg0", power-up level changed
    Info: Duplicate register "int:inst10|process0~2" merged to single register "int:inst10|process0~0"
    Info: Duplicate register "int:inst10|process0~35" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~69" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~33" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~31" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~29" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~27" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~25" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~23" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~21" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~19" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~17" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~15" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~13" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~10" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~67" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~65" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~63" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~61" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~59" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~57" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~55" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~53" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~51" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~49" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~47" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~45" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~43" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~41" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~39" merged to single register "int:inst10|process0~7"
    Info: Duplicate register "int:inst10|process0~37" merged to single register "int:inst10|process0~7"
Info: State machine "|test|int:inst10|state" contains 11 states
Info: Selected One-Hot state machine encoding method for state machine "|test|int:inst10|state"
Info: Encoding result for state machine "|test|int:inst10|state"
    Info: Completed encoding using 11 state bits
        Info: Encoded state bit "int:inst10|state.zz"
        Info: Encoded state bit "int:inst10|state.done2"
        Info: Encoded state bit "int:inst10|state.w3"
        Info: Encoded state bit "int:inst10|state.w2"
        Info: Encoded state bit "int:inst10|state.w1"
        Info: Encoded state bit "int:inst10|state.w0"
        Info: Encoded state bit "int:inst10|state.r4"
        Info: Encoded state bit "int:inst10|state.r3"
        Info: Encoded state bit "int:inst10|state.r2"
        Info: Encoded state bit "int:inst10|state.r1"
        Info: Encoded state bit "int:inst10|state.idle"
    Info: State "|test|int:inst10|state.idle" uses code string "00000000000"
    Info: State "|test|int:inst10|state.r1" uses code string "00000000011"
    Info: State "|test|int:inst10|state.r2" uses code string "00000000101"
    Info: State "|test|int:inst10|state.r3" uses code string "00000001001"
    Info: State "|test|int:inst10|state.r4" uses code string "00000010001"
    Info: State "|test|int:inst10|state.w0" uses code string "00000100001"
    Info: State "|test|int:inst10|state.w1" uses code string "00001000001"
    Info: State "|test|int:inst10|state.w2" uses code string "00010000001"
    Info: State "|test|int:inst10|state.w3" uses code string "00100000001"
    Info: State "|test|int:inst10|state.done2" uses code string "01000000001"
    Info: State "|test|int:inst10|state.zz" uses code string "10000000001"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "TEST" stuck at GND
Info: Registers with preset signals will power-up high
Warning: Output port clk0 of PLL "pllll:inst3|altpll:altpll_component|pll" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
Info: Implemented 205 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 7 output pins
    Info: Implemented 62 bidirectional pins
    Info: Implemented 131 logic cells
    Info: Implemented 1 ClockLock PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 70 warnings
    Info: Processing ended: Fri Oct 20 19:01:41 2006
    Info: Elapsed time: 00:00:09