📄 test.map.rpt
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; C4_USE_CASC_IN ; 0 ; Untyped ;
; C5_USE_CASC_IN ; 0 ; Untyped ;
; CLK0_COUNTER ; G0 ; Untyped ;
; CLK1_COUNTER ; G0 ; Untyped ;
; CLK2_COUNTER ; G0 ; Untyped ;
; CLK3_COUNTER ; G0 ; Untyped ;
; CLK4_COUNTER ; G0 ; Untyped ;
; CLK5_COUNTER ; G0 ; Untyped ;
; L0_TIME_DELAY ; 0 ; Untyped ;
; L1_TIME_DELAY ; 0 ; Untyped ;
; G0_TIME_DELAY ; 0 ; Untyped ;
; G1_TIME_DELAY ; 0 ; Untyped ;
; G2_TIME_DELAY ; 0 ; Untyped ;
; G3_TIME_DELAY ; 0 ; Untyped ;
; E0_TIME_DELAY ; 0 ; Untyped ;
; E1_TIME_DELAY ; 0 ; Untyped ;
; E2_TIME_DELAY ; 0 ; Untyped ;
; E3_TIME_DELAY ; 0 ; Untyped ;
; M_TIME_DELAY ; 0 ; Untyped ;
; N_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK3_COUNTER ; E3 ; Untyped ;
; EXTCLK2_COUNTER ; E2 ; Untyped ;
; EXTCLK1_COUNTER ; E1 ; Untyped ;
; EXTCLK0_COUNTER ; E0 ; Untyped ;
; ENABLE0_COUNTER ; L0 ; Untyped ;
; ENABLE1_COUNTER ; L0 ; Untyped ;
; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;
; LOOP_FILTER_R ; 1.000000 ; Untyped ;
; LOOP_FILTER_C ; 5 ; Untyped ;
; VCO_POST_SCALE ; 0 ; Untyped ;
; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; INTENDED_DEVICE_FAMILY ; Cyclone ; Untyped ;
; PORT_CLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKENA4 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKENA5 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLK0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLK1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLK2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLK3 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKBAD0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKBAD1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK3 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK4 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK5 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANDATA ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANDATAOUT ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANDONE ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ACTIVECLOCK ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKLOSS ; PORT_CONNECTIVITY ; Untyped ;
; PORT_INCLK1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_INCLK0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_FBIN ; PORT_CONNECTIVITY ; Untyped ;
; PORT_PLLENA ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKSWITCH ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ARESET ; PORT_CONNECTIVITY ; Untyped ;
; PORT_PFDENA ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANCLK ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANACLR ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANREAD ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANWRITE ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;
; M_TEST_SOURCE ; 5 ; Untyped ;
; C0_TEST_SOURCE ; 5 ; Untyped ;
; C1_TEST_SOURCE ; 5 ; Untyped ;
; C2_TEST_SOURCE ; 5 ; Untyped ;
; C3_TEST_SOURCE ; 5 ; Untyped ;
; C4_TEST_SOURCE ; 5 ; Untyped ;
; C5_TEST_SOURCE ; 5 ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+-------------------------------+-------------------+------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: bt:inst4|lpm_bustri:lpm_bustri_component ;
+----------------+-------+--------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+--------------------------------------------------------------+
; LPM_WIDTH ; 32 ; Integer ;
+----------------+-------+--------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/pci/reg_wr/test.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Fri Oct 20 19:01:34 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test -c test
Info: Found 1 design units, including 1 entities, in source file test.bdf
Info: Found entity 1: test
Info: Found 2 design units, including 1 entities, in source file int.vhd
Info: Found design unit 1: int-a
Info: Found entity 1: int
Info: Elaborating entity "test" for the top level hierarchy
Warning: Port "lint1" of type int and instance "inst10" is missing source signal
Warning: Port "lint2" of type int and instance "inst10" is missing source signal
Warning: Using design file pllll.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: pllll-SYN
Info: Found entity 1: pllll
Info: Elaborating entity "pllll" for hierarchy "pllll:inst3"
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus51/libraries/megafunctions/altpll.tdf
Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "pllll:inst3|altpll:altpll_component"
Info: Elaborating entity "int" for hierarchy "int:inst10"
Info (10035): Verilog HDL or VHDL information at int.vhd(23): object "tt" declared but not used
Warning (10036): Verilog HDL or VHDL warning at int.vhd(24): object "tc" assigned a value but never read
Warning (10034): Output port "lint2" at int.vhd(7) has no driver
Warning: Using design file bt.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: bt-SYN
Info: Found entity 1: bt
Info: Elaborating entity "bt" for hierarchy "bt:inst4"
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus51/libraries/megafunctions/lpm_bustri.tdf
Info: Found entity 1: lpm_bustri
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