test.map.eqn

altera公司的FPGA的一些开发用的VHDL的源代码用于学习

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--E1__clk0 is pllll:inst3|altpll:altpll_component|_clk0
E1__clk0 = PLL.CLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(SYSCLK), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());


--D1_lint1 is int:inst10|lint1
--operation mode is normal

D1_lint1_lut_out = D1_lint1 & !D1_state.done2 # !D1_state.idle;
D1_lint1 = DFFEAS(D1_lint1_lut_out, E1__clk0, VCC, , LRESETo_, , , , );


--D1L150Q is int:inst10|wr~reg0
--operation mode is normal

D1L150Q_lut_out = D1_state.w0;
D1L150Q = DFFEAS(D1L150Q_lut_out, E1__clk0, VCC, , D1L64, , , , );


--D1L63Q is int:inst10|process0~7
--operation mode is normal

D1L63Q_lut_out = D1_state.idle;
D1L63Q = DFFEAS(D1L63Q_lut_out, E1__clk0, VCC, , D1L64, , , , );


--D1L1Q is int:inst10|blast~reg0
--operation mode is normal

D1L1Q_lut_out = D1L2;
D1L1Q = DFFEAS(D1L1Q_lut_out, E1__clk0, VCC, , D1L66, , , , );


--D1L62Q is int:inst10|process0~4
--operation mode is normal

D1L62Q_lut_out = D1_state.idle;
D1L62Q = DFFEAS(D1L62Q_lut_out, E1__clk0, VCC, , D1L66, , , , );


--D1L3Q is int:inst10|ccs~reg0
--operation mode is normal

D1L3Q_lut_out = !D1L2;
D1L3Q = DFFEAS(D1L3Q_lut_out, E1__clk0, VCC, , D1L67, , , , );


--D1L61Q is int:inst10|process0~0
--operation mode is normal

D1L61Q_lut_out = D1_state.idle;
D1L61Q = DFFEAS(D1L61Q_lut_out, E1__clk0, VCC, , D1L67, , , , );


--D1_state.done2 is int:inst10|state.done2
--operation mode is normal

D1_state.done2_lut_out = D1_state.done2 & (inst2 # D1_state.w3 & !ready) # !D1_state.done2 & (D1_state.w3 & !ready);
D1_state.done2 = DFFEAS(D1_state.done2_lut_out, E1__clk0, LRESETo_, , , , , , );


--D1_state.idle is int:inst10|state.idle
--operation mode is normal

D1_state.idle_lut_out = inst2 # !D1_state.done2 & D1_state.idle;
D1_state.idle = DFFEAS(D1_state.idle_lut_out, E1__clk0, LRESETo_, , , , , , );


--D1_state.w0 is int:inst10|state.w0
--operation mode is normal

D1_state.w0_lut_out = D1_state.zz & A1L112 & A1L116;
D1_state.w0 = DFFEAS(D1_state.w0_lut_out, E1__clk0, LRESETo_, , , , , , );


--D1_state.r1 is int:inst10|state.r1
--operation mode is normal

D1_state.r1_lut_out = !D1_state.idle & (inst2);
D1_state.r1 = DFFEAS(D1_state.r1_lut_out, E1__clk0, LRESETo_, , , , , , );


--D1L64 is int:inst10|process0~258
--operation mode is normal

D1L64 = LRESETo_ & (D1_state.w0 # D1_state.r1 # !D1_state.idle);


--D1_state.r2 is int:inst10|state.r2
--operation mode is normal

D1_state.r2_lut_out = D1_state.r1;
D1_state.r2 = DFFEAS(D1_state.r2_lut_out, E1__clk0, LRESETo_, , , , , , );


--D1_state.w1 is int:inst10|state.w1
--operation mode is normal

D1_state.w1_lut_out = D1_state.w0;
D1_state.w1 = DFFEAS(D1_state.w1_lut_out, E1__clk0, LRESETo_, , , , , , );


--D1L2 is int:inst10|ccs~5
--operation mode is normal

D1L2 = !D1_state.r2 & !D1_state.w1;


--D1_state.r4 is int:inst10|state.r4
--operation mode is normal

D1_state.r4_lut_out = D1_state.r3 # D1_state.r4 & ready;
D1_state.r4 = DFFEAS(D1_state.r4_lut_out, E1__clk0, LRESETo_, , , , , , );


--D1_state.w3 is int:inst10|state.w3
--operation mode is normal

D1_state.w3_lut_out = D1_state.w2 # D1_state.w3 & ready;
D1_state.w3 = DFFEAS(D1_state.w3_lut_out, E1__clk0, LRESETo_, , , , , , );


--D1L65 is int:inst10|process0~259
--operation mode is normal

D1L65 = LRESETo_ & (!D1_state.r4 & !D1_state.w3 # !ready);


--D1L68 is int:inst10|reduce_or~49
--operation mode is normal

D1L68 = D1_state.idle & (!D1_state.r2 & !D1_state.w1);


--D1L66 is int:inst10|process0~260
--operation mode is normal

D1L66 = D1L65 & (D1_state.r4 # D1_state.w3 # !D1L68);


--D1L67 is int:inst10|process0~261
--operation mode is normal

D1L67 = LRESETo_ & (D1_state.w0 # D1_state.r1 # !D1L68);


--inst2 is inst2
--operation mode is normal

inst2_lut_out = inst1;
inst2 = DFFEAS(inst2_lut_out, E1__clk0, LRESETo_, , , , , , );


--D1_t_dout[31] is int:inst10|t_dout[31]
--operation mode is normal

D1_t_dout[31]_lut_out = D1_tempd1[31];
D1_t_dout[31] = DFFEAS(D1_t_dout[31]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_s2 is int:inst10|s2
--operation mode is normal

D1_s2_lut_out = D1_state.zz # D1_state.idle & D1_s2;
D1_s2 = DFFEAS(D1_s2_lut_out, E1__clk0, LRESETo_, , , , , , );


--D1_t_dout[30] is int:inst10|t_dout[30]
--operation mode is normal

D1_t_dout[30]_lut_out = D1_tempd1[30];
D1_t_dout[30] = DFFEAS(D1_t_dout[30]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[29] is int:inst10|t_dout[29]
--operation mode is normal

D1_t_dout[29]_lut_out = D1_tempd1[29];
D1_t_dout[29] = DFFEAS(D1_t_dout[29]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[28] is int:inst10|t_dout[28]
--operation mode is normal

D1_t_dout[28]_lut_out = D1_tempd1[28];
D1_t_dout[28] = DFFEAS(D1_t_dout[28]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[27] is int:inst10|t_dout[27]
--operation mode is normal

D1_t_dout[27]_lut_out = D1_tempd1[27];
D1_t_dout[27] = DFFEAS(D1_t_dout[27]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[26] is int:inst10|t_dout[26]
--operation mode is normal

D1_t_dout[26]_lut_out = D1_tempd1[26];
D1_t_dout[26] = DFFEAS(D1_t_dout[26]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[25] is int:inst10|t_dout[25]
--operation mode is normal

D1_t_dout[25]_lut_out = D1_tempd1[25];
D1_t_dout[25] = DFFEAS(D1_t_dout[25]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[24] is int:inst10|t_dout[24]
--operation mode is normal

D1_t_dout[24]_lut_out = D1_tempd1[24];
D1_t_dout[24] = DFFEAS(D1_t_dout[24]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[23] is int:inst10|t_dout[23]
--operation mode is normal

D1_t_dout[23]_lut_out = D1_tempd1[23];
D1_t_dout[23] = DFFEAS(D1_t_dout[23]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[22] is int:inst10|t_dout[22]
--operation mode is normal

D1_t_dout[22]_lut_out = D1_tempd1[22];
D1_t_dout[22] = DFFEAS(D1_t_dout[22]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[21] is int:inst10|t_dout[21]
--operation mode is normal

D1_t_dout[21]_lut_out = D1_tempd1[21];
D1_t_dout[21] = DFFEAS(D1_t_dout[21]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[20] is int:inst10|t_dout[20]
--operation mode is normal

D1_t_dout[20]_lut_out = D1_tempd1[20];
D1_t_dout[20] = DFFEAS(D1_t_dout[20]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[19] is int:inst10|t_dout[19]
--operation mode is normal

D1_t_dout[19]_lut_out = D1_tempd1[19];
D1_t_dout[19] = DFFEAS(D1_t_dout[19]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[18] is int:inst10|t_dout[18]
--operation mode is normal

D1_t_dout[18]_lut_out = D1_tempd1[18];
D1_t_dout[18] = DFFEAS(D1_t_dout[18]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[17] is int:inst10|t_dout[17]
--operation mode is normal

D1_t_dout[17]_lut_out = D1_tempd1[17];
D1_t_dout[17] = DFFEAS(D1_t_dout[17]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[16] is int:inst10|t_dout[16]
--operation mode is normal

D1_t_dout[16]_lut_out = D1_tempd1[16];
D1_t_dout[16] = DFFEAS(D1_t_dout[16]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[15] is int:inst10|t_dout[15]
--operation mode is normal

D1_t_dout[15]_lut_out = D1_tempd1[15];
D1_t_dout[15] = DFFEAS(D1_t_dout[15]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[14] is int:inst10|t_dout[14]
--operation mode is normal

D1_t_dout[14]_lut_out = D1_tempd1[14];
D1_t_dout[14] = DFFEAS(D1_t_dout[14]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[13] is int:inst10|t_dout[13]
--operation mode is normal

D1_t_dout[13]_lut_out = D1_tempd1[13];
D1_t_dout[13] = DFFEAS(D1_t_dout[13]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[12] is int:inst10|t_dout[12]
--operation mode is normal

D1_t_dout[12]_lut_out = D1_tempd1[12];
D1_t_dout[12] = DFFEAS(D1_t_dout[12]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[11] is int:inst10|t_dout[11]
--operation mode is normal

D1_t_dout[11]_lut_out = D1_tempd1[11];
D1_t_dout[11] = DFFEAS(D1_t_dout[11]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[10] is int:inst10|t_dout[10]
--operation mode is normal

D1_t_dout[10]_lut_out = D1_tempd1[10];
D1_t_dout[10] = DFFEAS(D1_t_dout[10]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[9] is int:inst10|t_dout[9]
--operation mode is normal

D1_t_dout[9]_lut_out = D1_tempd1[9];
D1_t_dout[9] = DFFEAS(D1_t_dout[9]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[8] is int:inst10|t_dout[8]
--operation mode is normal

D1_t_dout[8]_lut_out = D1_tempd1[8];
D1_t_dout[8] = DFFEAS(D1_t_dout[8]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[7] is int:inst10|t_dout[7]
--operation mode is normal

D1_t_dout[7]_lut_out = D1_tempd1[7];
D1_t_dout[7] = DFFEAS(D1_t_dout[7]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[6] is int:inst10|t_dout[6]
--operation mode is normal

D1_t_dout[6]_lut_out = D1_tempd1[6];
D1_t_dout[6] = DFFEAS(D1_t_dout[6]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[5] is int:inst10|t_dout[5]
--operation mode is normal

D1_t_dout[5]_lut_out = D1_tempd1[5];
D1_t_dout[5] = DFFEAS(D1_t_dout[5]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[4] is int:inst10|t_dout[4]
--operation mode is normal

D1_t_dout[4]_lut_out = D1_tempd1[4];
D1_t_dout[4] = DFFEAS(D1_t_dout[4]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[3] is int:inst10|t_dout[3]
--operation mode is normal

D1_t_dout[3]_lut_out = D1_tempd1[3];
D1_t_dout[3] = DFFEAS(D1_t_dout[3]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[2] is int:inst10|t_dout[2]
--operation mode is normal

D1_t_dout[2]_lut_out = D1_tempd1[2];
D1_t_dout[2] = DFFEAS(D1_t_dout[2]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[1] is int:inst10|t_dout[1]
--operation mode is normal

D1_t_dout[1]_lut_out = D1_tempd1[1];
D1_t_dout[1] = DFFEAS(D1_t_dout[1]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_t_dout[0] is int:inst10|t_dout[0]
--operation mode is normal

D1_t_dout[0]_lut_out = D1_tempd1[0];
D1_t_dout[0] = DFFEAS(D1_t_dout[0]_lut_out, E1__clk0, VCC, , D1L114, , , , );


--D1_state.zz is int:inst10|state.zz
--operation mode is normal

D1_state.zz_lut_out = D1L149 # D1_state.zz & (!A1L116 # !A1L112);
D1_state.zz = DFFEAS(D1_state.zz_lut_out, E1__clk0, LRESETo_, , , , , , );


--D1_count[0] is int:inst10|count[0]
--operation mode is arithmetic

D1_count[0]_lut_out = !D1_count[0];
D1_count[0] = DFFEAS(D1_count[0]_lut_out, E1__clk0, LRESETo_, , D1_state.zz, , , , );

--D1L6 is int:inst10|count[0]~253
--operation mode is arithmetic

D1L6 = CARRY(D1_count[0]);


--D1_count[1] is int:inst10|count[1]
--operation mode is arithmetic

D1_count[1]_carry_eqn = D1L6;
D1_count[1]_lut_out = D1_count[1] $ (D1_count[1]_carry_eqn);
D1_count[1] = DFFEAS(D1_count[1]_lut_out, E1__clk0, LRESETo_, , D1_state.zz, , , , );

--D1L8 is int:inst10|count[1]~257
--operation mode is arithmetic

D1L8 = CARRY(!D1L6 # !D1_count[1]);


--D1_count[2] is int:inst10|count[2]
--operation mode is arithmetic

D1_count[2]_carry_eqn = D1L8;
D1_count[2]_lut_out = D1_count[2] $ (!D1_count[2]_carry_eqn);
D1_count[2] = DFFEAS(D1_count[2]_lut_out, E1__clk0, LRESETo_, , D1_state.zz, , , , );

--D1L10 is int:inst10|count[2]~261
--operation mode is arithmetic

D1L10 = CARRY(D1_count[2] & (!D1L8));


--D1_count[3] is int:inst10|count[3]
--operation mode is arithmetic

D1_count[3]_carry_eqn = D1L10;
D1_count[3]_lut_out = D1_count[3] $ (D1_count[3]_carry_eqn);
D1_count[3] = DFFEAS(D1_count[3]_lut_out, E1__clk0, LRESETo_, , D1_state.zz, , , , );

--D1L12 is int:inst10|count[3]~265
--operation mode is arithmetic

D1L12 = CARRY(!D1L10 # !D1_count[3]);


--A1L108 is rtl~238
--operation mode is normal

A1L108 = D1_count[0] & D1_count[1] & D1_count[2] & D1_count[3];


--D1_count[4] is int:inst10|count[4]
--operation mode is arithmetic

D1_count[4]_carry_eqn = D1L12;
D1_count[4]_lut_out = D1_count[4] $ (!D1_count[4]_carry_eqn);
D1_count[4] = DFFEAS(D1_count[4]_lut_out, E1__clk0, LRESETo_, , D1_state.zz, , , , );

--D1L14 is int:inst10|count[4]~269
--operation mode is arithmetic

D1L14 = CARRY(D1_count[4] & (!D1L12));


--D1_count[5] is int:inst10|count[5]
--operation mode is arithmetic

D1_count[5]_carry_eqn = D1L14;
D1_count[5]_lut_out = D1_count[5] $ (D1_count[5]_carry_eqn);
D1_count[5] = DFFEAS(D1_count[5]_lut_out, E1__clk0, LRESETo_, , D1_state.zz, , , , );

--D1L16 is int:inst10|count[5]~273
--operation mode is arithmetic

D1L16 = CARRY(!D1L14 # !D1_count[5]);


--D1_count[6] is int:inst10|count[6]
--operation mode is arithmetic

D1_count[6]_carry_eqn = D1L16;
D1_count[6]_lut_out = D1_count[6] $ (!D1_count[6]_carry_eqn);
D1_count[6] = DFFEAS(D1_count[6]_lut_out, E1__clk0, LRESETo_, , D1_state.zz, , , , );

--D1L18 is int:inst10|count[6]~277
--operation mode is arithmetic

D1L18 = CARRY(D1_count[6] & (!D1L16));


--D1_count[7] is int:inst10|count[7]
--operation mode is arithmetic

D1_count[7]_carry_eqn = D1L18;
D1_count[7]_lut_out = D1_count[7] $ (D1_count[7]_carry_eqn);
D1_count[7] = DFFEAS(D1_count[7]_lut_out, E1__clk0, LRESETo_, , D1_state.zz, , , , );

--D1L20 is int:inst10|count[7]~281
--operation mode is arithmetic

D1L20 = CARRY(!D1L18 # !D1_count[7]);


--A1L109 is rtl~239
--operation mode is normal

A1L109 = D1_count[4] & D1_count[5] & D1_count[6] & D1_count[7];


--D1_count[8] is int:inst10|count[8]
--operation mode is arithmetic

D1_count[8]_carry_eqn = D1L20;
D1_count[8]_lut_out = D1_count[8] $ (!D1_count[8]_carry_eqn);
D1_count[8] = DFFEAS(D1_count[8]_lut_out, E1__clk0, LRESETo_, , D1_state.zz, , , , );

--D1L22 is int:inst10|count[8]~285
--operation mode is arithmetic

D1L22 = CARRY(D1_count[8] & (!D1L20));


--D1_count[9] is int:inst10|count[9]
--operation mode is arithmetic

D1_count[9]_carry_eqn = D1L22;
D1_count[9]_lut_out = D1_count[9] $ (D1_count[9]_carry_eqn);
D1_count[9] = DFFEAS(D1_count[9]_lut_out, E1__clk0, LRESETo_, , D1_state.zz, , , , );

--D1L24 is int:inst10|count[9]~289
--operation mode is arithmetic

D1L24 = CARRY(!D1L22 # !D1_count[9]);


--D1_count[10] is int:inst10|count[10]
--operation mode is arithmetic

D1_count[10]_carry_eqn = D1L24;
D1_count[10]_lut_out = D1_count[10] $ (!D1_count[10]_carry_eqn);
D1_count[10] = DFFEAS(D1_count[10]_lut_out, E1__clk0, LRESETo_, , D1_state.zz, , , , );

--D1L26 is int:inst10|count[10]~293
--operation mode is arithmetic

D1L26 = CARRY(D1_count[10] & (!D1L24));


--D1_count[11] is int:inst10|count[11]
--operation mode is arithmetic

D1_count[11]_carry_eqn = D1L26;
D1_count[11]_lut_out = D1_count[11] $ (D1_count[11]_carry_eqn);
D1_count[11] = DFFEAS(D1_count[11]_lut_out, E1__clk0, LRESETo_, , D1_state.zz, , , , );

--D1L28 is int:inst10|count[11]~297
--operation mode is arithmetic

D1L28 = CARRY(!D1L26 # !D1_count[11]);


--A1L110 is rtl~240
--operation mode is normal