test.hier_info

altera公司的FPGA的一些开发用的VHDL的源代码用于学习

|test
TEST <= <GND>
LCLK <= clk.DB_MAX_OUTPUT_PORT_TYPE
SYSCLK => pllll:inst3.inclk0
LW/R_ <= int:inst10.wr
LINT => inst1.DATAIN
LRESETo_ => inst1.PRESET
LRESETo_ => inst2.PRESET
LRESETo_ => int:inst10.rst
ready => int:inst10.ready
LD[0] <= bt:inst4.tridata[0]
LD[1] <= bt:inst4.tridata[1]
LD[2] <= bt:inst4.tridata[2]
LD[3] <= bt:inst4.tridata[3]
LD[4] <= bt:inst4.tridata[4]
LD[5] <= bt:inst4.tridata[5]
LD[6] <= bt:inst4.tridata[6]
LD[7] <= bt:inst4.tridata[7]
LD[8] <= bt:inst4.tridata[8]
LD[9] <= bt:inst4.tridata[9]
LD[10] <= bt:inst4.tridata[10]
LD[11] <= bt:inst4.tridata[11]
LD[12] <= bt:inst4.tridata[12]
LD[13] <= bt:inst4.tridata[13]
LD[14] <= bt:inst4.tridata[14]
LD[15] <= bt:inst4.tridata[15]
LD[16] <= bt:inst4.tridata[16]
LD[17] <= bt:inst4.tridata[17]
LD[18] <= bt:inst4.tridata[18]
LD[19] <= bt:inst4.tridata[19]
LD[20] <= bt:inst4.tridata[20]
LD[21] <= bt:inst4.tridata[21]
LD[22] <= bt:inst4.tridata[22]
LD[23] <= bt:inst4.tridata[23]
LD[24] <= bt:inst4.tridata[24]
LD[25] <= bt:inst4.tridata[25]
LD[26] <= bt:inst4.tridata[26]
LD[27] <= bt:inst4.tridata[27]
LD[28] <= bt:inst4.tridata[28]
LD[29] <= bt:inst4.tridata[29]
LD[30] <= bt:inst4.tridata[30]
LD[31] <= bt:inst4.tridata[31]
BLAST_ <= int:inst10.blast
ADS_ <= int:inst10.ads
CCS_ <= int:inst10.ccs
leed <= int:inst10.lint1
LA[2] <= int:inst10.la[2]
LA[3] <= int:inst10.la[3]
LA[4] <= int:inst10.la[4]
LA[5] <= int:inst10.la[5]
LA[6] <= int:inst10.la[6]
LA[7] <= int:inst10.la[7]
LA[8] <= int:inst10.la[8]
LA[9] <= int:inst10.la[9]
LA[10] <= int:inst10.la[10]
LA[11] <= int:inst10.la[11]
LA[12] <= int:inst10.la[12]
LA[13] <= int:inst10.la[13]
LA[14] <= int:inst10.la[14]
LA[15] <= int:inst10.la[15]
LA[16] <= int:inst10.la[16]
LA[17] <= int:inst10.la[17]
LA[18] <= int:inst10.la[18]
LA[19] <= int:inst10.la[19]
LA[20] <= int:inst10.la[20]
LA[21] <= int:inst10.la[21]
LA[22] <= int:inst10.la[22]
LA[23] <= int:inst10.la[23]
LA[24] <= int:inst10.la[24]
LA[25] <= int:inst10.la[25]
LA[26] <= int:inst10.la[26]
LA[27] <= int:inst10.la[27]
LA[28] <= int:inst10.la[28]
LA[29] <= int:inst10.la[29]
LA[30] <= int:inst10.la[30]
LA[31] <= int:inst10.la[31]


|test|pllll:inst3
inclk0 => altpll:altpll_component.inclk[0]
c0 <= altpll:altpll_component.clk[0]


|test|pllll:inst3|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => pll.CLK1
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
clk[0] <= pll.CLK
clk[1] <= <UNC>
clk[2] <= <UNC>
clk[3] <= <UNC>
clk[4] <= <UNC>
clk[5] <= <UNC>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= <GND>


|test|int:inst10
lint => Select~3.IN4
lint => state~11.OUTPUTSELECT
lint => state~12.OUTPUTSELECT
lint => state~13.OUTPUTSELECT
lint => state~14.OUTPUTSELECT
lint => state~15.OUTPUTSELECT
lint => state~16.OUTPUTSELECT
lint => state~17.OUTPUTSELECT
lint => state~18.OUTPUTSELECT
lint => state~19.OUTPUTSELECT
lint => state~20.OUTPUTSELECT
lint => state~21.OUTPUTSELECT
lint => Select~4.IN1
clk => count[27].CLK
clk => count[26].CLK
clk => count[25].CLK
clk => count[24].CLK
clk => count[23].CLK
clk => count[22].CLK
clk => count[21].CLK
clk => count[20].CLK
clk => count[19].CLK
clk => count[18].CLK
clk => count[17].CLK
clk => count[16].CLK
clk => count[15].CLK
clk => count[14].CLK
clk => count[13].CLK
clk => count[12].CLK
clk => count[11].CLK
clk => count[10].CLK
clk => count[9].CLK
clk => count[8].CLK
clk => count[7].CLK
clk => count[6].CLK
clk => count[5].CLK
clk => count[4].CLK
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => s1~reg0.CLK
clk => s2~reg0.CLK
clk => ccs~reg0.CLK
clk => ads~reg0.CLK
clk => blast~reg0.CLK
clk => wr~reg0.CLK
clk => lint1~reg0.CLK
clk => la[31]~reg0.CLK
clk => la[30]~reg0.CLK
clk => la[29]~reg0.CLK
clk => la[28]~reg0.CLK
clk => la[27]~reg0.CLK
clk => la[26]~reg0.CLK
clk => la[25]~reg0.CLK
clk => la[24]~reg0.CLK
clk => la[23]~reg0.CLK
clk => la[22]~reg0.CLK
clk => la[21]~reg0.CLK
clk => la[20]~reg0.CLK
clk => la[19]~reg0.CLK
clk => la[18]~reg0.CLK
clk => la[17]~reg0.CLK
clk => la[16]~reg0.CLK
clk => la[15]~reg0.CLK
clk => la[14]~reg0.CLK
clk => la[13]~reg0.CLK
clk => la[12]~reg0.CLK
clk => la[11]~reg0.CLK
clk => la[10]~reg0.CLK
clk => la[9]~reg0.CLK
clk => la[8]~reg0.CLK
clk => la[7]~reg0.CLK
clk => la[6]~reg0.CLK
clk => la[5]~reg0.CLK
clk => la[4]~reg0.CLK
clk => la[3]~reg0.CLK
clk => la[2]~reg0.CLK
clk => tempd1[31].CLK
clk => tempd1[30].CLK
clk => tempd1[29].CLK
clk => tempd1[28].CLK
clk => tempd1[27].CLK
clk => tempd1[26].CLK
clk => tempd1[25].CLK
clk => tempd1[24].CLK
clk => tempd1[23].CLK
clk => tempd1[22].CLK
clk => tempd1[21].CLK
clk => tempd1[20].CLK
clk => tempd1[19].CLK
clk => tempd1[18].CLK
clk => tempd1[17].CLK
clk => tempd1[16].CLK
clk => tempd1[15].CLK
clk => tempd1[14].CLK
clk => tempd1[13].CLK
clk => tempd1[12].CLK
clk => tempd1[11].CLK
clk => tempd1[10].CLK
clk => tempd1[9].CLK
clk => tempd1[8].CLK
clk => tempd1[7].CLK
clk => tempd1[6].CLK
clk => tempd1[5].CLK
clk => tempd1[4].CLK
clk => tempd1[3].CLK
clk => tempd1[2].CLK
clk => tempd1[1].CLK
clk => tempd1[0].CLK
clk => t_dout[31].CLK
clk => t_dout[30].CLK
clk => t_dout[29].CLK
clk => t_dout[28].CLK
clk => t_dout[27].CLK
clk => t_dout[26].CLK
clk => t_dout[25].CLK
clk => t_dout[24].CLK
clk => t_dout[23].CLK
clk => t_dout[22].CLK
clk => t_dout[21].CLK
clk => t_dout[20].CLK
clk => t_dout[19].CLK
clk => t_dout[18].CLK
clk => t_dout[17].CLK
clk => t_dout[16].CLK
clk => t_dout[15].CLK
clk => t_dout[14].CLK
clk => t_dout[13].CLK
clk => t_dout[12].CLK
clk => t_dout[11].CLK
clk => t_dout[10].CLK
clk => t_dout[9].CLK
clk => t_dout[8].CLK
clk => t_dout[7].CLK
clk => t_dout[6].CLK
clk => t_dout[5].CLK
clk => t_dout[4].CLK
clk => t_dout[3].CLK
clk => t_dout[2].CLK
clk => t_dout[1].CLK
clk => t_dout[0].CLK
clk => process0~0.CLK
clk => process0~2.CLK
clk => process0~4.CLK
clk => process0~7.CLK
clk => process0~10.CLK
clk => process0~13.CLK
clk => process0~15.CLK
clk => process0~17.CLK
clk => process0~19.CLK
clk => process0~21.CLK
clk => process0~23.CLK
clk => process0~25.CLK
clk => process0~27.CLK
clk => process0~29.CLK
clk => process0~31.CLK
clk => process0~33.CLK
clk => process0~35.CLK
clk => process0~37.CLK
clk => process0~39.CLK
clk => process0~41.CLK
clk => process0~43.CLK
clk => process0~45.CLK
clk => process0~47.CLK
clk => process0~49.CLK
clk => process0~51.CLK
clk => process0~53.CLK
clk => process0~55.CLK
clk => process0~57.CLK
clk => process0~59.CLK
clk => process0~61.CLK
clk => process0~63.CLK
clk => process0~65.CLK
clk => process0~67.CLK
clk => process0~69.CLK
clk => state~22.IN1
rst => process0~1.IN0
rst => process0~6.IN0
rst => process0~9.IN0
rst => process0~12.IN0
rst => count[27].ACLR
rst => count[26].ACLR
rst => count[25].ACLR
rst => count[24].ACLR
rst => count[23].ACLR
rst => count[22].ACLR
rst => count[21].ACLR
rst => count[20].ACLR
rst => count[19].ACLR
rst => count[18].ACLR
rst => count[17].ACLR
rst => count[16].ACLR
rst => count[15].ACLR
rst => count[14].ACLR
rst => count[13].ACLR
rst => count[12].ACLR
rst => count[11].ACLR
rst => count[10].ACLR
rst => count[9].ACLR
rst => count[8].ACLR
rst => count[7].ACLR
rst => count[6].ACLR
rst => count[5].ACLR
rst => count[4].ACLR
rst => count[3].ACLR
rst => count[2].ACLR
rst => count[1].ACLR
rst => count[0].ACLR
rst => s1~reg0.ACLR
rst => s2~reg0.ACLR
rst => lint1~reg0.ENA
rst => state~23.IN1
lint1 <= lint1~reg0.DB_MAX_OUTPUT_PORT_TYPE
lint2 <= <GND>
ready => Select~7.IN5
ready => Select~11.IN5
ready => Select~12.IN1
ready => Select~13.IN1
ready => Select~14.IN3
ready => Select~14.IN4
ccs <= process0~3.DB_MAX_OUTPUT_PORT_TYPE
ads <= process0~5.DB_MAX_OUTPUT_PORT_TYPE
blast <= process0~8.DB_MAX_OUTPUT_PORT_TYPE
wr <= process0~11.DB_MAX_OUTPUT_PORT_TYPE
la[2] <= process0~71.DB_MAX_OUTPUT_PORT_TYPE
la[3] <= process0~70.DB_MAX_OUTPUT_PORT_TYPE
la[4] <= process0~68.DB_MAX_OUTPUT_PORT_TYPE
la[5] <= process0~66.DB_MAX_OUTPUT_PORT_TYPE