test.map.qmsg

altera公司的FPGA的一些开发用的VHDL的源代码用于学习

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "int:inst10\|la\[4\]~reg0 data_in GND " "Warning: Reduced register \"int:inst10\|la\[4\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "int:inst10\|la\[2\]~reg0 data_in GND " "Warning: Reduced register \"int:inst10\|la\[2\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[31\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[31\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[30\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[30\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[29\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[29\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[28\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[28\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[27\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[27\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[26\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[26\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[25\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[25\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[24\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[24\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[23\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[23\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[22\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[22\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[21\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[21\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[20\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[20\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[19\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[19\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[18\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[18\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[17\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[17\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[16\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[16\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[15\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[15\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[14\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[14\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[13\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[13\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[12\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[12\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[11\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[11\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[10\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[10\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[9\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[9\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[8\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[8\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[7\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[7\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[6\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[6\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[5\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[5\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[4\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[4\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[3\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[3\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[2\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[2\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[1\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[1\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[0\] " "Warning: Converting TRI node \"bt:inst4\|lpm_bustri:lpm_bustri_component\|din\[0\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0}  } {  } 0 0 "Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|ads~reg0 int:inst10\|ccs~reg0 " "Info: Duplicate register \"int:inst10\|ads~reg0\" merged to single register \"int:inst10\|ccs~reg0\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 9 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|la\[5\]~reg0 int:inst10\|wr~reg0 " "Info: Duplicate register \"int:inst10\|la\[5\]~reg0\" merged to single register \"int:inst10\|wr~reg0\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "int:inst10\|la\[3\]~reg0 int:inst10\|wr~reg0 " "Info: Duplicate register \"int:inst10\|la\[3\]~reg0\" merged to single register \"int:inst10\|wr~reg0\", power-up level changed" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~2 int:inst10\|process0~0 " "Info: Duplicate register \"int:inst10\|process0~2\" merged to single register \"int:inst10\|process0~0\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~35 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~35\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~69 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~69\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~33 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~33\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~31 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~31\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~29 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~29\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~27 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~27\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~25 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~25\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~23 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~23\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~21 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~21\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~19 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~19\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~17 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~17\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~15 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~15\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~13 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~13\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~10 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~10\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~67 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~67\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~65 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~65\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~63 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~63\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~61 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~61\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~59 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~59\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~57 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~57\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~55 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~55\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~53 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~53\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~51 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~51\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~49 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~49\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~47 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~47\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~45 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~45\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~43 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~43\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~41 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~41\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~39 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~39\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "int:inst10\|process0~37 int:inst10\|process0~7 " "Info: Duplicate register \"int:inst10\|process0~37\" merged to single register \"int:inst10\|process0~7\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|test\|int:inst10\|state 11 " "Info: State machine \"\|test\|int:inst10\|state\" contains 11 states" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 20 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "One-Hot \|test\|int:inst10\|state " "Info: Selected One-Hot state machine encoding method for state machine \"\|test\|int:inst10\|state\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 20 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|test\|int:inst10\|state " "Info: Encoding result for state machine \"\|test\|int:inst10\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "11 " "Info: Completed encoding using 11 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "int:inst10\|state.zz " "Info: Encoded state bit \"int:inst10\|state.zz\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "int:inst10\|state.done2 " "Info: Encoded state bit \"int:inst10\|state.done2\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "int:inst10\|state.w3 " "Info: Encoded state bit \"int:inst10\|state.w3\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "int:inst10\|state.w2 " "Info: Encoded state bit \"int:inst10\|state.w2\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "int:inst10\|state.w1 " "Info: Encoded state bit \"int:inst10\|state.w1\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "int:inst10\|state.w0 " "Info: Encoded state bit \"int:inst10\|state.w0\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "int:inst10\|state.r4 " "Info: Encoded state bit \"int:inst10\|state.r4\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "int:inst10\|state.r3 " "Info: Encoded state bit \"int:inst10\|state.r3\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "int:inst10\|state.r2 " "Info: Encoded state bit \"int:inst10\|state.r2\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "int:inst10\|state.r1 " "Info: Encoded state bit \"int:inst10\|state.r1\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "int:inst10\|state.idle " "Info: Encoded state bit \"int:inst10\|state.idle\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|test\|int:inst10\|state.idle 00000000000 " "Info: State \"\|test\|int:inst10\|state.idle\" uses code string \"00000000000\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|test\|int:inst10\|state.r1 00000000011 " "Info: State \"\|test\|int:inst10\|state.r1\" uses code string \"00000000011\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|test\|int:inst10\|state.r2 00000000101 " "Info: State \"\|test\|int:inst10\|state.r2\" uses code string \"00000000101\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|test\|int:inst10\|state.r3 00000001001 " "Info: State \"\|test\|int:inst10\|state.r3\" uses code string \"00000001001\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|test\|int:inst10\|state.r4 00000010001 " "Info: State \"\|test\|int:inst10\|state.r4\" uses code string \"00000010001\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|test\|int:inst10\|state.w0 00000100001 " "Info: State \"\|test\|int:inst10\|state.w0\" uses code string \"00000100001\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|test\|int:inst10\|state.w1 00001000001 " "Info: State \"\|test\|int:inst10\|state.w1\" uses code string \"00001000001\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|test\|int:inst10\|state.w2 00010000001 " "Info: State \"\|test\|int:inst10\|state.w2\" uses code string \"00010000001\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|test\|int:inst10\|state.w3 00100000001 " "Info: State \"\|test\|int:inst10\|state.w3\" uses code string \"00100000001\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|test\|int:inst10\|state.done2 01000000001 " "Info: State \"\|test\|int:inst10\|state.done2\" uses code string \"01000000001\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|test\|int:inst10\|state.zz 10000000001 " "Info: State \"\|test\|int:inst10\|state.zz\" uses code string \"10000000001\"" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 20 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "TEST GND " "Warning: Pin \"TEST\" stuck at GND" {  } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 232 248 424 248 "TEST" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 120 1288 1352 200 "inst2" "" } } } } { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 120 1200 1264 200 "inst1" "" } } } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Warning" "WCUT_CUT_YGR_PLL_BAD_FANOUT_CLK3" "clk0 pllll:inst3\|altpll:altpll_component\|pll " "Warning: Output port clk0 of PLL \"pllll:inst3\|altpll:altpll_component\|pll\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "pllll.vhd" "" { Text "C:/pci/reg_wr/pllll.vhd" 93 -1 0 } } { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 368 128 400 528 "inst3" "" } } } }  } 0 0 "Output port %1!s! of PLL \"%2!s!\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "205 " "Info: Implemented 205 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "7 " "Info: Implemented 7 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "62 " "Info: Implemented 62 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "131 " "Info: Implemented 131 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0 0 "Implemented %1!d! ClockLock PLLs" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 70 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 70 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 20 19:01:41 2006 " "Info: Processing ended: Fri Oct 20 19:01:41 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}