test.map.qmsg

altera公司的FPGA的一些开发用的VHDL的源代码用于学习

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 20 19:01:34 2006 " "Info: Processing started: Fri Oct 20 19:01:34 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off test -c test " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test -c test" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file test.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 test " "Info: Found entity 1: test" {  } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "int.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file int.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 int-a " "Info: Found design unit 1: int-a" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 18 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 int " "Info: Found entity 1: int" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "test " "Info: Elaborating entity \"test\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "lint1 int inst10 " "Warning: Port \"lint1\" of type int and instance \"inst10\" is missing source signal" {  } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 288 1384 1552 512 "inst10" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "lint2 int inst10 " "Warning: Port \"lint2\" of type int and instance \"inst10\" is missing source signal" {  } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 288 1384 1552 512 "inst10" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "pllll.vhd 2 1 " "Warning: Using design file pllll.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pllll-SYN " "Info: Found design unit 1: pllll-SYN" {  } { { "pllll.vhd" "" { Text "C:/pci/reg_wr/pllll.vhd" 54 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 pllll " "Info: Found entity 1: pllll" {  } { { "pllll.vhd" "" { Text "C:/pci/reg_wr/pllll.vhd" 45 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pllll pllll:inst3 " "Info: Elaborating entity \"pllll\" for hierarchy \"pllll:inst3\"" {  } { { "test.bdf" "inst3" { Schematic "C:/pci/reg_wr/test.bdf" { { 368 128 400 528 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../altera/quartus51/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus51/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altpll.tdf" 363 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll pllll:inst3\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"pllll:inst3\|altpll:altpll_component\"" {  } { { "pllll.vhd" "altpll_component" { Text "C:/pci/reg_wr/pllll.vhd" 93 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "int int:inst10 " "Info: Elaborating entity \"int\" for hierarchy \"int:inst10\"" {  } { { "test.bdf" "inst10" { Schematic "C:/pci/reg_wr/test.bdf" { { 288 1384 1552 512 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "tt int.vhd(23) " "Info (10035): Verilog HDL or VHDL information at int.vhd(23): object \"tt\" declared but not used" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 23 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "tc int.vhd(24) " "Warning (10036): Verilog HDL or VHDL warning at int.vhd(24): object \"tc\" assigned a value but never read" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 24 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "lint2 int.vhd(7) " "Warning (10034): Output port \"lint2\" at int.vhd(7) has no driver" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 7 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}