test.hif

altera公司的FPGA的一些开发用的VHDL的源代码用于学习

DEF
C5_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
CLK0_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK1_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK2_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK3_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK4_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK5_COUNTER
G0
PARAMETER_UNKNOWN
DEF
L0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
L1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
M_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
N_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_COUNTER
E3
PARAMETER_UNKNOWN
DEF
EXTCLK2_COUNTER
E2
PARAMETER_UNKNOWN
DEF
EXTCLK1_COUNTER
E1
PARAMETER_UNKNOWN
DEF
EXTCLK0_COUNTER
E0
PARAMETER_UNKNOWN
DEF
ENABLE0_COUNTER
L0
PARAMETER_UNKNOWN
DEF
ENABLE1_COUNTER
L0
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT
2
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R
 1.000000
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C
5
PARAMETER_UNKNOWN
DEF
VCO_POST_SCALE
0
PARAMETER_UNKNOWN
DEF
CLK2_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK1_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK0_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
PORT_CLKENA0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA4
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA5
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKBAD0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKBAD1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK4
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK5
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANDATA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANDATAOUT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANDONE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCLKOUT1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCLKOUT0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ACTIVECLOCK
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKLOSS
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_INCLK1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_INCLK0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_FBIN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PLLENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKSWITCH
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ARESET
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PFDENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANCLK
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANACLR
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANREAD
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANWRITE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclk0
-1
3
clk0
-1
3
inclk1
-1
1
}
# include_file {
..|..|altera|quartus51|libraries|megafunctions|aglobal51.inc
79bc6dd52df42999c126c3949d5fedc
..|..|altera|quartus51|libraries|megafunctions|stratix_pll.inc
5f8211898149ceae8264a0ea5036254f
..|..|altera|quartus51|libraries|megafunctions|stratixii_pll.inc
6d1985e16ab5f59a1fd6b0ae20978a4e
..|..|altera|quartus51|libraries|megafunctions|cycloneii_pll.inc
39a0d9d1237d1db39c848c3f9faffc
}
# hierarchies {
pllll:inst3|altpll:altpll_component
}
# end
# entity
bt
# storage
db|test.(4).cnf
db|test.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
bt.vhd
7da636c6f2671ed072c3ee2682f3d28
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
bt:inst4
}
# end
# entity
lpm_bustri
# storage
db|test.(5).cnf
db|test.(5).cnf
# case_insensitive
# source_file
..|..|altera|quartus51|libraries|megafunctions|lpm_bustri.tdf
ed9464e1998de88a81948be961c1d04b
6
# user_parameter {
LPM_WIDTH
32
PARAMETER_DEC
USR
}
# used_port {
tridata9
-1
3
tridata8
-1
3
tridata7
-1
3
tridata6
-1
3
tridata5
-1
3
tridata4
-1
3
tridata31
-1
3
tridata30
-1
3
tridata3
-1
3
tridata29
-1
3
tridata28
-1
3
tridata27
-1
3
tridata26
-1
3
tridata25
-1
3
tridata24
-1
3
tridata23
-1
3
tridata22
-1
3
tridata21
-1
3
tridata20
-1
3
tridata2
-1
3
tridata19
-1
3
tridata18
-1
3
tridata17
-1
3
tridata16
-1
3
tridata15
-1
3
tridata14
-1
3
tridata13
-1
3
tridata12
-1
3
tridata11
-1
3
tridata10
-1
3
tridata1
-1
3
tridata0
-1
3
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result31
-1
3
result30
-1
3
result3
-1
3
result29
-1
3
result28
-1
3
result27
-1
3
result26
-1
3
result25
-1
3
result24
-1
3
result23
-1
3
result22
-1
3
result21
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
enabletr
-1
3
enabledt
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data31
-1
3
data30
-1
3
data3
-1
3
data29
-1
3
data28
-1
3
data27
-1
3
data26
-1
3
data25
-1
3
data24
-1
3
data23
-1
3
data22
-1
3
data21
-1
3
data20
-1
3
data2
-1
3
data19
-1
3
data18
-1
3
data17
-1
3
data16
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
bt:inst4|lpm_bustri:lpm_bustri_component
}
# end
# entity
test
# storage
db|test.(0).cnf
db|test.(0).cnf
# case_insensitive
# source_file
test.bdf
69c25e5922f2569bc85a930539a6e1b
23
# hierarchies {
|
}
# end
# entity
int
# storage
db|test.(3).cnf
db|test.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
int.vhd
8b257fab5d2e2760e2ff2dd5e48ae8
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
int:inst10
}
# end
# complete