test.tan.qmsg

altera公司的FPGA的一些开发用的VHDL的源代码用于学习

{ "Info" "ITDB_TSU_RESULT" "int:inst10\|t_dout\[9\] LRESETo_ SYSCLK 12.197 ns register " "Info: tsu for register \"int:inst10\|t_dout\[9\]\" (data pin = \"LRESETo_\", clock pin = \"SYSCLK\") is 12.197 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.680 ns + Longest pin register " "Info: + Longest pin to register delay is 12.680 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns LRESETo_ 1 PIN PIN_178 48 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_178; Fanout = 48; PIN Node = 'LRESETo_'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LRESETo_ } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 344 1088 1256 360 "LRESETo_" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.296 ns) + CELL(0.590 ns) 9.355 ns int:inst10\|t_dout\[31\]~0 2 COMB LC_X15_Y14_N0 32 " "Info: 2: + IC(7.296 ns) + CELL(0.590 ns) = 9.355 ns; Loc. = LC_X15_Y14_N0; Fanout = 32; COMB Node = 'int:inst10\|t_dout\[31\]~0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "7.886 ns" { LRESETo_ int:inst10|t_dout[31]~0 } "NODE_NAME" } "" } } { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.458 ns) + CELL(0.867 ns) 12.680 ns int:inst10\|t_dout\[9\] 3 REG LC_X22_Y20_N4 1 " "Info: 3: + IC(2.458 ns) + CELL(0.867 ns) = 12.680 ns; Loc. = LC_X22_Y20_N4; Fanout = 1; REG Node = 'int:inst10\|t_dout\[9\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "3.325 ns" { int:inst10|t_dout[31]~0 int:inst10|t_dout[9] } "NODE_NAME" } "" } } { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.926 ns ( 23.08 % ) " "Info: Total cell delay = 2.926 ns ( 23.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.754 ns ( 76.92 % ) " "Info: Total interconnect delay = 9.754 ns ( 76.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "12.680 ns" { LRESETo_ int:inst10|t_dout[31]~0 int:inst10|t_dout[9] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.680 ns" { LRESETo_ LRESETo_~out0 int:inst10|t_dout[31]~0 int:inst10|t_dout[9] } { 0.000ns 0.000ns 7.296ns 2.458ns } { 0.000ns 1.469ns 0.590ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_PLL_OFFSET" "SYSCLK pllll:inst3\|altpll:altpll_component\|_clk0 -1.885 ns - " "Info: - Offset between input clock \"SYSCLK\" and output clock \"pllll:inst3\|altpll:altpll_component\|_clk0\" is -1.885 ns" {  } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 424 -96 72 440 "SYSCLK" "" } } } } { "altpll.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pllll:inst3\|altpll:altpll_component\|_clk0 destination 2.405 ns - Shortest register " "Info: - Shortest clock path from clock \"pllll:inst3\|altpll:altpll_component\|_clk0\" to destination register is 2.405 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pllll:inst3\|altpll:altpll_component\|_clk0 1 CLK PLL_2 114 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 114; CLK Node = 'pllll:inst3\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { pllll:inst3|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.694 ns) + CELL(0.711 ns) 2.405 ns int:inst10\|t_dout\[9\] 2 REG LC_X22_Y20_N4 1 " "Info: 2: + IC(1.694 ns) + CELL(0.711 ns) = 2.405 ns; Loc. = LC_X22_Y20_N4; Fanout = 1; REG Node = 'int:inst10\|t_dout\[9\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.405 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|t_dout[9] } "NODE_NAME" } "" } } { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 29.56 % ) " "Info: Total cell delay = 0.711 ns ( 29.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.694 ns ( 70.44 % ) " "Info: Total interconnect delay = 1.694 ns ( 70.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.405 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|t_dout[9] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.405 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|t_dout[9] } { 0.000ns 1.694ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "12.680 ns" { LRESETo_ int:inst10|t_dout[31]~0 int:inst10|t_dout[9] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.680 ns" { LRESETo_ LRESETo_~out0 int:inst10|t_dout[31]~0 int:inst10|t_dout[9] } { 0.000ns 0.000ns 7.296ns 2.458ns } { 0.000ns 1.469ns 0.590ns 0.867ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.405 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|t_dout[9] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.405 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|t_dout[9] } { 0.000ns 1.694ns } { 0.000ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "SYSCLK LW/R_ int:inst10\|process0~7 9.008 ns register " "Info: tco from clock \"SYSCLK\" to destination pin \"LW/R_\" through register \"int:inst10\|process0~7\" is 9.008 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "SYSCLK pllll:inst3\|altpll:altpll_component\|_clk0 -1.885 ns + " "Info: + Offset between input clock \"SYSCLK\" and output clock \"pllll:inst3\|altpll:altpll_component\|_clk0\" is -1.885 ns" {  } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 424 -96 72 440 "SYSCLK" "" } } } } { "altpll.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pllll:inst3\|altpll:altpll_component\|_clk0 source 2.397 ns + Longest register " "Info: + Longest clock path from clock \"pllll:inst3\|altpll:altpll_component\|_clk0\" to source register is 2.397 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pllll:inst3\|altpll:altpll_component\|_clk0 1 CLK PLL_2 114 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 114; CLK Node = 'pllll:inst3\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { pllll:inst3|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.686 ns) + CELL(0.711 ns) 2.397 ns int:inst10\|process0~7 2 REG LC_X16_Y14_N5 31 " "Info: 2: + IC(1.686 ns) + CELL(0.711 ns) = 2.397 ns; Loc. = LC_X16_Y14_N5; Fanout = 31; REG Node = 'int:inst10\|process0~7'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|process0~7 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 29.66 % ) " "Info: Total cell delay = 0.711 ns ( 29.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.686 ns ( 70.34 % ) " "Info: Total interconnect delay = 1.686 ns ( 70.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|process0~7 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|process0~7 } { 0.000ns 1.686ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.272 ns + Longest register pin " "Info: + Longest register to pin delay is 8.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int:inst10\|process0~7 1 REG LC_X16_Y14_N5 31 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y14_N5; Fanout = 31; REG Node = 'int:inst10\|process0~7'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { int:inst10|process0~7 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.193 ns) + CELL(2.079 ns) 8.272 ns LW/R_ 2 PIN PIN_240 0 " "Info: 2: + IC(6.193 ns) + CELL(2.079 ns) = 8.272 ns; Loc. = PIN_240; Fanout = 0; PIN Node = 'LW/R_'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "8.272 ns" { int:inst10|process0~7 LW/R_ } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 392 1584 1760 408 "LW/R_" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.079 ns ( 25.13 % ) " "Info: Total cell delay = 2.079 ns ( 25.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.193 ns ( 74.87 % ) " "Info: Total interconnect delay = 6.193 ns ( 74.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "8.272 ns" { int:inst10|process0~7 LW/R_ } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.272 ns" { int:inst10|process0~7 LW/R_ } { 0.000ns 6.193ns } { 0.000ns 2.079ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|process0~7 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|process0~7 } { 0.000ns 1.686ns } { 0.000ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "8.272 ns" { int:inst10|process0~7 LW/R_ } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.272 ns" { int:inst10|process0~7 LW/R_ } { 0.000ns 6.193ns } { 0.000ns 2.079ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "int:inst10\|tempd1\[7\] LD\[7\] SYSCLK -6.078 ns register " "Info: th for register \"int:inst10\|tempd1\[7\]\" (data pin = \"LD\[7\]\", clock pin = \"SYSCLK\") is -6.078 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "SYSCLK pllll:inst3\|altpll:altpll_component\|_clk0 -1.885 ns + " "Info: + Offset between input clock \"SYSCLK\" and output clock \"pllll:inst3\|altpll:altpll_component\|_clk0\" is -1.885 ns" {  } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 424 -96 72 440 "SYSCLK" "" } } } } { "altpll.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pllll:inst3\|altpll:altpll_component\|_clk0 destination 2.405 ns + Longest register " "Info: + Longest clock path from clock \"pllll:inst3\|altpll:altpll_component\|_clk0\" to destination register is 2.405 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pllll:inst3\|altpll:altpll_component\|_clk0 1 CLK PLL_2 114 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 114; CLK Node = 'pllll:inst3\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { pllll:inst3|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.694 ns) + CELL(0.711 ns) 2.405 ns int:inst10\|tempd1\[7\] 2 REG LC_X22_Y20_N8 1 " "Info: 2: + IC(1.694 ns) + CELL(0.711 ns) = 2.405 ns; Loc. = LC_X22_Y20_N8; Fanout = 1; REG Node = 'int:inst10\|tempd1\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.405 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|tempd1[7] } "NODE_NAME" } "" } } { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 29.56 % ) " "Info: Total cell delay = 0.711 ns ( 29.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.694 ns ( 70.44 % ) " "Info: Total interconnect delay = 1.694 ns ( 70.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.405 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|tempd1[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.405 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|tempd1[7] } { 0.000ns 1.694ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.613 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.613 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LD\[7\] 1 PIN PIN_203 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_203; Fanout = 1; PIN Node = 'LD\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[7] } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns LD~24 2 COMB IOC_X22_Y21_N0 1 " "Info: 2: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = IOC_X22_Y21_N0; Fanout = 1; COMB Node = 'LD~24'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "1.475 ns" { LD[7] LD~24 } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.023 ns) + CELL(0.115 ns) 6.613 ns int:inst10\|tempd1\[7\] 3 REG LC_X22_Y20_N8 1 " "Info: 3: + IC(5.023 ns) + CELL(0.115 ns) = 6.613 ns; Loc. = LC_X22_Y20_N8; Fanout = 1; REG Node = 'int:inst10\|tempd1\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "5.138 ns" { LD~24 int:inst10|tempd1[7] } "NODE_NAME" } "" } } { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.590 ns ( 24.04 % ) " "Info: Total cell delay = 1.590 ns ( 24.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.023 ns ( 75.96 % ) " "Info: Total interconnect delay = 5.023 ns ( 75.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "6.613 ns" { LD[7] LD~24 int:inst10|tempd1[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.613 ns" { LD[7] LD~24 int:inst10|tempd1[7] } { 0.000ns 0.000ns 5.023ns } { 0.000ns 1.475ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.405 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|tempd1[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.405 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|tempd1[7] } { 0.000ns 1.694ns } { 0.000ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "6.613 ns" { LD[7] LD~24 int:inst10|tempd1[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.613 ns" { LD[7] LD~24 int:inst10|tempd1[7] } { 0.000ns 0.000ns 5.023ns } { 0.000ns 1.475ns 0.115ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "SYSCLK LCLK pllll:inst3\|altpll:altpll_component\|_clk0 2.803 ns clock " "Info: Minimum tco from clock \"SYSCLK\" to destination pin \"LCLK\" through clock \"pllll:inst3\|altpll:altpll_component\|_clk0\" is 2.803 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "SYSCLK pllll:inst3\|altpll:altpll_component\|_clk0 -1.885 ns + " "Info: + Offset between input clock \"SYSCLK\" and output clock \"pllll:inst3\|altpll:altpll_component\|_clk0\" is -1.885 ns" {  } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 424 -96 72 440 "SYSCLK" "" } } } } { "altpll.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.688 ns + Shortest clock pin " "Info: + Shortest clock to pin delay is 4.688 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pllll:inst3\|altpll:altpll_component\|_clk0 1 CLK PLL_2 114 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 114; CLK Node = 'pllll:inst3\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { pllll:inst3|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.580 ns) + CELL(2.108 ns) 4.688 ns LCLK 2 PIN PIN_187 0 " "Info: 2: + IC(2.580 ns) + CELL(2.108 ns) = 4.688 ns; Loc. = PIN_187; Fanout = 0; PIN Node = 'LCLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "4.688 ns" { pllll:inst3|altpll:altpll_component|_clk0 LCLK } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 280 248 424 296 "LCLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 44.97 % ) " "Info: Total cell delay = 2.108 ns ( 44.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.580 ns ( 55.03 % ) " "Info: Total interconnect delay = 2.580 ns ( 55.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "4.688 ns" { pllll:inst3|altpll:altpll_component|_clk0 LCLK } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.688 ns" { pllll:inst3|altpll:altpll_component|_clk0 LCLK } { 0.000ns 2.580ns } { 0.000ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "4.688 ns" { pllll:inst3|altpll:altpll_component|_clk0 LCLK } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.688 ns" { pllll:inst3|altpll:altpll_component|_clk0 LCLK } { 0.000ns 2.580ns } { 0.000ns 2.108ns } } }  } 0 0 "Minimum tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}