test.tan.qmsg

altera公司的FPGA的一些开发用的VHDL的源代码用于学习

{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "pllll:inst3\|altpll:altpll_component\|_clk0 register int:inst10\|state.idle register int:inst10\|wr~reg0 28.464 ns " "Info: Slack time is 28.464 ns for clock \"pllll:inst3\|altpll:altpll_component\|_clk0\" between source register \"int:inst10\|state.idle\" and destination register \"int:inst10\|wr~reg0\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "205.38 MHz 4.869 ns " "Info: Fmax is 205.38 MHz (period= 4.869 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "33.072 ns + Largest register register " "Info: + Largest register to register requirement is 33.072 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "33.333 ns + " "Info: + Setup relationship between source and destination is 33.333 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 31.448 ns " "Info: + Latch edge is 31.448 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pllll:inst3\|altpll:altpll_component\|_clk0 33.333 ns -1.885 ns  50 " "Info: Clock period of Destination clock \"pllll:inst3\|altpll:altpll_component\|_clk0\" is 33.333 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.885 ns " "Info: - Launch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pllll:inst3\|altpll:altpll_component\|_clk0 33.333 ns -1.885 ns  50 " "Info: Clock period of Source clock \"pllll:inst3\|altpll:altpll_component\|_clk0\" is 33.333 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pllll:inst3\|altpll:altpll_component\|_clk0 destination 2.397 ns + Shortest register " "Info: + Shortest clock path from clock \"pllll:inst3\|altpll:altpll_component\|_clk0\" to destination register is 2.397 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pllll:inst3\|altpll:altpll_component\|_clk0 1 CLK PLL_2 114 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 114; CLK Node = 'pllll:inst3\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { pllll:inst3|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.686 ns) + CELL(0.711 ns) 2.397 ns int:inst10\|wr~reg0 2 REG LC_X16_Y14_N9 3 " "Info: 2: + IC(1.686 ns) + CELL(0.711 ns) = 2.397 ns; Loc. = LC_X16_Y14_N9; Fanout = 3; REG Node = 'int:inst10\|wr~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|wr~reg0 } "NODE_NAME" } "" } } { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 29.66 % ) " "Info: Total cell delay = 0.711 ns ( 29.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.686 ns ( 70.34 % ) " "Info: Total interconnect delay = 1.686 ns ( 70.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|wr~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|wr~reg0 } { 0.000ns 1.686ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pllll:inst3\|altpll:altpll_component\|_clk0 source 2.397 ns - Longest register " "Info: - Longest clock path from clock \"pllll:inst3\|altpll:altpll_component\|_clk0\" to source register is 2.397 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pllll:inst3\|altpll:altpll_component\|_clk0 1 CLK PLL_2 114 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 114; CLK Node = 'pllll:inst3\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { pllll:inst3|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.686 ns) + CELL(0.711 ns) 2.397 ns int:inst10\|state.idle 2 REG LC_X15_Y14_N4 9 " "Info: 2: + IC(1.686 ns) + CELL(0.711 ns) = 2.397 ns; Loc. = LC_X15_Y14_N4; Fanout = 9; REG Node = 'int:inst10\|state.idle'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|state.idle } "NODE_NAME" } "" } } { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 29.66 % ) " "Info: Total cell delay = 0.711 ns ( 29.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.686 ns ( 70.34 % ) " "Info: Total interconnect delay = 1.686 ns ( 70.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|state.idle } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|state.idle } { 0.000ns 1.686ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|wr~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|wr~reg0 } { 0.000ns 1.686ns } { 0.000ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|state.idle } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|state.idle } { 0.000ns 1.686ns } { 0.000ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|wr~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|wr~reg0 } { 0.000ns 1.686ns } { 0.000ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|state.idle } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|state.idle } { 0.000ns 1.686ns } { 0.000ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.608 ns - Longest register register " "Info: - Longest register to register delay is 4.608 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int:inst10\|state.idle 1 REG LC_X15_Y14_N4 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y14_N4; Fanout = 9; REG Node = 'int:inst10\|state.idle'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { int:inst10|state.idle } "NODE_NAME" } "" } } { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.880 ns) + CELL(0.590 ns) 2.470 ns int:inst10\|process0~258 2 COMB LC_X16_Y13_N5 2 " "Info: 2: + IC(1.880 ns) + CELL(0.590 ns) = 2.470 ns; Loc. = LC_X16_Y13_N5; Fanout = 2; COMB Node = 'int:inst10\|process0~258'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.470 ns" { int:inst10|state.idle int:inst10|process0~258 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.271 ns) + CELL(0.867 ns) 4.608 ns int:inst10\|wr~reg0 3 REG LC_X16_Y14_N9 3 " "Info: 3: + IC(1.271 ns) + CELL(0.867 ns) = 4.608 ns; Loc. = LC_X16_Y14_N9; Fanout = 3; REG Node = 'int:inst10\|wr~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.138 ns" { int:inst10|process0~258 int:inst10|wr~reg0 } "NODE_NAME" } "" } } { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.457 ns ( 31.62 % ) " "Info: Total cell delay = 1.457 ns ( 31.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.151 ns ( 68.38 % ) " "Info: Total interconnect delay = 3.151 ns ( 68.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "4.608 ns" { int:inst10|state.idle int:inst10|process0~258 int:inst10|wr~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.608 ns" { int:inst10|state.idle int:inst10|process0~258 int:inst10|wr~reg0 } { 0.000ns 1.880ns 1.271ns } { 0.000ns 0.590ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|wr~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|wr~reg0 } { 0.000ns 1.686ns } { 0.000ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|state.idle } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|state.idle } { 0.000ns 1.686ns } { 0.000ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "4.608 ns" { int:inst10|state.idle int:inst10|process0~258 int:inst10|wr~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.608 ns" { int:inst10|state.idle int:inst10|process0~258 int:inst10|wr~reg0 } { 0.000ns 1.880ns 1.271ns } { 0.000ns 0.590ns 0.867ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "SYSCLK " "Info: No valid register-to-register data paths exist for clock \"SYSCLK\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "pllll:inst3\|altpll:altpll_component\|_clk0 register int:inst10\|tempd1\[1\] register int:inst10\|t_dout\[1\] 860 ps " "Info: Minimum slack time is 860 ps for clock \"pllll:inst3\|altpll:altpll_component\|_clk0\" between source register \"int:inst10\|tempd1\[1\]\" and destination register \"int:inst10\|t_dout\[1\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.651 ns + Shortest register register " "Info: + Shortest register to register delay is 0.651 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int:inst10\|tempd1\[1\] 1 REG LC_X14_Y20_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y20_N9; Fanout = 1; REG Node = 'int:inst10\|tempd1\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { int:inst10|tempd1[1] } "NODE_NAME" } "" } } { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.536 ns) + CELL(0.115 ns) 0.651 ns int:inst10\|t_dout\[1\] 2 REG LC_X14_Y20_N4 1 " "Info: 2: + IC(0.536 ns) + CELL(0.115 ns) = 0.651 ns; Loc. = LC_X14_Y20_N4; Fanout = 1; REG Node = 'int:inst10\|t_dout\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "0.651 ns" { int:inst10|tempd1[1] int:inst10|t_dout[1] } "NODE_NAME" } "" } } { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns ( 17.67 % ) " "Info: Total cell delay = 0.115 ns ( 17.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.536 ns ( 82.33 % ) " "Info: Total interconnect delay = 0.536 ns ( 82.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "0.651 ns" { int:inst10|tempd1[1] int:inst10|t_dout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "0.651 ns" { int:inst10|tempd1[1] int:inst10|t_dout[1] } { 0.000ns 0.536ns } { 0.000ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -1.885 ns " "Info: + Latch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pllll:inst3\|altpll:altpll_component\|_clk0 33.333 ns -1.885 ns  50 " "Info: Clock period of Destination clock \"pllll:inst3\|altpll:altpll_component\|_clk0\" is 33.333 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.885 ns " "Info: - Launch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pllll:inst3\|altpll:altpll_component\|_clk0 33.333 ns -1.885 ns  50 " "Info: Clock period of Source clock \"pllll:inst3\|altpll:altpll_component\|_clk0\" is 33.333 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pllll:inst3\|altpll:altpll_component\|_clk0 destination 2.397 ns + Longest register " "Info: + Longest clock path from clock \"pllll:inst3\|altpll:altpll_component\|_clk0\" to destination register is 2.397 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pllll:inst3\|altpll:altpll_component\|_clk0 1 CLK PLL_2 114 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 114; CLK Node = 'pllll:inst3\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { pllll:inst3|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.686 ns) + CELL(0.711 ns) 2.397 ns int:inst10\|t_dout\[1\] 2 REG LC_X14_Y20_N4 1 " "Info: 2: + IC(1.686 ns) + CELL(0.711 ns) = 2.397 ns; Loc. = LC_X14_Y20_N4; Fanout = 1; REG Node = 'int:inst10\|t_dout\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|t_dout[1] } "NODE_NAME" } "" } } { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 29.66 % ) " "Info: Total cell delay = 0.711 ns ( 29.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.686 ns ( 70.34 % ) " "Info: Total interconnect delay = 1.686 ns ( 70.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|t_dout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|t_dout[1] } { 0.000ns 1.686ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pllll:inst3\|altpll:altpll_component\|_clk0 source 2.397 ns - Shortest register " "Info: - Shortest clock path from clock \"pllll:inst3\|altpll:altpll_component\|_clk0\" to source register is 2.397 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pllll:inst3\|altpll:altpll_component\|_clk0 1 CLK PLL_2 114 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 114; CLK Node = 'pllll:inst3\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { pllll:inst3|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.686 ns) + CELL(0.711 ns) 2.397 ns int:inst10\|tempd1\[1\] 2 REG LC_X14_Y20_N9 1 " "Info: 2: + IC(1.686 ns) + CELL(0.711 ns) = 2.397 ns; Loc. = LC_X14_Y20_N9; Fanout = 1; REG Node = 'int:inst10\|tempd1\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|tempd1[1] } "NODE_NAME" } "" } } { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 29.66 % ) " "Info: Total cell delay = 0.711 ns ( 29.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.686 ns ( 70.34 % ) " "Info: Total interconnect delay = 1.686 ns ( 70.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|tempd1[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|tempd1[1] } { 0.000ns 1.686ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|t_dout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|t_dout[1] } { 0.000ns 1.686ns } { 0.000ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|tempd1[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|tempd1[1] } { 0.000ns 1.686ns } { 0.000ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|t_dout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|t_dout[1] } { 0.000ns 1.686ns } { 0.000ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|tempd1[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|tempd1[1] } { 0.000ns 1.686ns } { 0.000ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "0.651 ns" { int:inst10|tempd1[1] int:inst10|t_dout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "0.651 ns" { int:inst10|tempd1[1] int:inst10|t_dout[1] } { 0.000ns 0.536ns } { 0.000ns 0.115ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|t_dout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|t_dout[1] } { 0.000ns 1.686ns } { 0.000ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|tempd1[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.397 ns" { pllll:inst3|altpll:altpll_component|_clk0 int:inst10|tempd1[1] } { 0.000ns 1.686ns } { 0.000ns 0.711ns } } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}