📄 test.fit.qmsg
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{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" { } { } 0 0 "Completed %1!s!" 0 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning: Following 3 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "TEST GND " "Info: Pin TEST has GND driving its datain port" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 232 248 424 248 "TEST" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "TEST" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { TEST } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { TEST } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LA\[7\] VCC " "Info: Pin LA\[7\] has VCC driving its datain port" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[7\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[7] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LA\[6\] VCC " "Info: Pin LA\[6\] has VCC driving its datain port" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[6\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[6] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IFSAC_FSAC_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "int:inst10\|s2 " "Info: Following pins have the same output enable: int:inst10\|s2" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[31\] LVTTL " "Info: Type bidirectional pin LD\[31\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[31\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[31] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[31] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[30\] LVTTL " "Info: Type bidirectional pin LD\[30\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[30\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[30] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[30] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[29\] LVTTL " "Info: Type bidirectional pin LD\[29\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[29\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[29] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[29] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[28\] LVTTL " "Info: Type bidirectional pin LD\[28\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[28\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[28] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[28] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[27\] LVTTL " "Info: Type bidirectional pin LD\[27\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[27\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[27] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[27] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[26\] LVTTL " "Info: Type bidirectional pin LD\[26\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[26\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[26] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[26] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[25\] LVTTL " "Info: Type bidirectional pin LD\[25\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[25\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[25] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[25] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[24\] LVTTL " "Info: Type bidirectional pin LD\[24\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[24\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[24] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[24] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[23\] LVTTL " "Info: Type bidirectional pin LD\[23\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[23\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[23] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[23] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[22\] LVTTL " "Info: Type bidirectional pin LD\[22\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[22\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[22] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[22] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[21\] LVTTL " "Info: Type bidirectional pin LD\[21\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[21\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[21] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[21] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[20\] LVTTL " "Info: Type bidirectional pin LD\[20\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[20\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[20] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[20] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[19\] LVTTL " "Info: Type bidirectional pin LD\[19\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[19\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[19] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[19] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[18\] LVTTL " "Info: Type bidirectional pin LD\[18\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[18\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[18] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[18] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[17\] LVTTL " "Info: Type bidirectional pin LD\[17\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[17\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[17] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[17] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[16\] LVTTL " "Info: Type bidirectional pin LD\[16\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[16\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[16] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[16] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[15\] LVTTL " "Info: Type bidirectional pin LD\[15\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[15\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[15] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[15] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[14\] LVTTL " "Info: Type bidirectional pin LD\[14\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[14\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[14] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[14] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[13\] LVTTL " "Info: Type bidirectional pin LD\[13\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[13\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[13] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[13] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[12\] LVTTL " "Info: Type bidirectional pin LD\[12\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[12\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[12] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[12] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[11\] LVTTL " "Info: Type bidirectional pin LD\[11\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[11\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[11] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[11] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[10\] LVTTL " "Info: Type bidirectional pin LD\[10\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[10\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[10] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[10] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[9\] LVTTL " "Info: Type bidirectional pin LD\[9\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[9\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[9] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[9] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[8\] LVTTL " "Info: Type bidirectional pin LD\[8\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[8\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[8] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[8] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[7\] LVTTL " "Info: Type bidirectional pin LD\[7\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[7\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[7] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[7] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[6\] LVTTL " "Info: Type bidirectional pin LD\[6\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[6\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[6] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[6] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[5\] LVTTL " "Info: Type bidirectional pin LD\[5\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[5\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[5] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[5] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[4\] LVTTL " "Info: Type bidirectional pin LD\[4\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[4\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[4] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[4] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[3\] LVTTL " "Info: Type bidirectional pin LD\[3\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[3\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[3] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[3] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[2\] LVTTL " "Info: Type bidirectional pin LD\[2\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[2\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[2] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[2] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[1\] LVTTL " "Info: Type bidirectional pin LD\[1\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[1\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[1] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[1] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LD\[0\] LVTTL " "Info: Type bidirectional pin LD\[0\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 584 1728 1904 600 "LD\[31..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LD\[0\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LD[0] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LD[0] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} } { } 0 0 "Following pins have the same output enable: %1!s!" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "int:inst10\|process0~7 " "Info: Following pins have the same output enable: int:inst10\|process0~7" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[31\] LVTTL " "Info: Type bidirectional pin LA\[31\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[31\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[31] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[31] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[30\] LVTTL " "Info: Type bidirectional pin LA\[30\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[30\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[30] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[30] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[29\] LVTTL " "Info: Type bidirectional pin LA\[29\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[29\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[29] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[29] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[28\] LVTTL " "Info: Type bidirectional pin LA\[28\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[28\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[28] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[28] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[27\] LVTTL " "Info: Type bidirectional pin LA\[27\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[27\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[27] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[27] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[26\] LVTTL " "Info: Type bidirectional pin LA\[26\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[26\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[26] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[26] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[25\] LVTTL " "Info: Type bidirectional pin LA\[25\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[25\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[25] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[25] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[24\] LVTTL " "Info: Type bidirectional pin LA\[24\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[24\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[24] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[24] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[23\] LVTTL " "Info: Type bidirectional pin LA\[23\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[23\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[23] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[23] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[22\] LVTTL " "Info: Type bidirectional pin LA\[22\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[22\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[22] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[22] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[21\] LVTTL " "Info: Type bidirectional pin LA\[21\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[21\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[21] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[21] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[20\] LVTTL " "Info: Type bidirectional pin LA\[20\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[20\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[20] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[20] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[19\] LVTTL " "Info: Type bidirectional pin LA\[19\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[19\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[19] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[19] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[18\] LVTTL " "Info: Type bidirectional pin LA\[18\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[18\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[18] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[18] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[17\] LVTTL " "Info: Type bidirectional pin LA\[17\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[17\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[17] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[17] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[16\] LVTTL " "Info: Type bidirectional pin LA\[16\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[16\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[16] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[16] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[15\] LVTTL " "Info: Type bidirectional pin LA\[15\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[15\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[15] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[15] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[14\] LVTTL " "Info: Type bidirectional pin LA\[14\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[14\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[14] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[14] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[13\] LVTTL " "Info: Type bidirectional pin LA\[13\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[13\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[13] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[13] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[12\] LVTTL " "Info: Type bidirectional pin LA\[12\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[12\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[12] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[12] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[11\] LVTTL " "Info: Type bidirectional pin LA\[11\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[11\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[11] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[11] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[10\] LVTTL " "Info: Type bidirectional pin LA\[10\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[10\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[10] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[10] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[9\] LVTTL " "Info: Type bidirectional pin LA\[9\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[9\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[9] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[9] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[8\] LVTTL " "Info: Type bidirectional pin LA\[8\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LA\[8\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LA[8] } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LA[8] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional LA\[7\] LVTTL " "Info: Type bidirectional pin LA\[7\] uses the LVTTL I/O standard" { } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 408 1584 1760 424 "LA\[31..2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/al⌨️ 快捷键说明
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