test.fit.qmsg

altera公司的FPGA的一些开发用的VHDL的源代码用于学习

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.188 ns register register " "Info: Estimated most critical path is register to register delay of 4.188 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int:inst10\|state.r4 1 REG LAB_X15_Y14 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y14; Fanout = 5; REG Node = 'int:inst10\|state.r4'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { int:inst10|state.r4 } "NODE_NAME" } "" } } { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.043 ns) + CELL(0.442 ns) 1.485 ns int:inst10\|tempd1\[31\]~0 2 COMB LAB_X14_Y18 32 " "Info: 2: + IC(1.043 ns) + CELL(0.442 ns) = 1.485 ns; Loc. = LAB_X14_Y18; Fanout = 32; COMB Node = 'int:inst10\|tempd1\[31\]~0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "1.485 ns" { int:inst10|state.r4 int:inst10|tempd1[31]~0 } "NODE_NAME" } "" } } { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.836 ns) + CELL(0.867 ns) 4.188 ns int:inst10\|tempd1\[9\] 3 REG LAB_X22_Y20 1 " "Info: 3: + IC(1.836 ns) + CELL(0.867 ns) = 4.188 ns; Loc. = LAB_X22_Y20; Fanout = 1; REG Node = 'int:inst10\|tempd1\[9\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "2.703 ns" { int:inst10|tempd1[31]~0 int:inst10|tempd1[9] } "NODE_NAME" } "" } } { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.309 ns ( 31.26 % ) " "Info: Total cell delay = 1.309 ns ( 31.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.879 ns ( 68.74 % ) " "Info: Total interconnect delay = 2.879 ns ( 68.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "4.188 ns" { int:inst10|state.r4 int:inst10|tempd1[31]~0 int:inst10|tempd1[9] } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 3 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 3%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}