test.fit.qmsg

altera公司的FPGA的一些开发用的VHDL的源代码用于学习

{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK_USER" "pllll:inst3\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"pllll:inst3\|altpll:altpll_component\|_clk0\" to use global clock (user assigned)" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "pllll:inst3\|altpll:altpll_component\|_clk0" } { 0 "pllll:inst3\|altpll:altpll_component\|_clk0" } } } } { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 368 128 400 528 "inst3" "" } } } } { "altpll.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { pllll:inst3|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { pllll:inst3|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock (user assigned)" 0 0}  } {  } 0 0 "Promoted PLL clock signals" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "LRESETo_ Global clock " "Info: Automatically promoted some destinations of signal \"LRESETo_\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "int:inst10\|lint1 " "Info: Destination \"int:inst10\|lint1\" may be non-global or may not use global clock" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 7 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "int:inst10\|process0~258 " "Info: Destination \"int:inst10\|process0~258\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "int:inst10\|process0~259 " "Info: Destination \"int:inst10\|process0~259\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "int:inst10\|process0~261 " "Info: Destination \"int:inst10\|process0~261\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "int:inst10\|t_dout\[31\]~0 " "Info: Destination \"int:inst10\|t_dout\[31\]~0\" may be non-global or may not use global clock" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "int:inst10\|tempd1\[31\]~0 " "Info: Destination \"int:inst10\|tempd1\[31\]~0\" may be non-global or may not use global clock" {  } { { "int.vhd" "" { Text "C:/pci/reg_wr/int.vhd" 32 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 344 1088 1256 360 "LRESETo_" "" } } } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "LRESETo_ " "Info: Pin \"LRESETo_\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "test.bdf" "" { Schematic "C:/pci/reg_wr/test.bdf" { { 344 1088 1256 360 "LRESETo_" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LRESETo_" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "test" "UNKNOWN" "V1" "C:/pci/reg_wr/db/test.quartus_db" { Floorplan "C:/pci/reg_wr/" "" "" { LRESETo_ } "NODE_NAME" } "" } } { "C:/pci/reg_wr/test.fld" "" { Floorplan "C:/pci/reg_wr/test.fld" "" "" { LRESETo_ } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}