test.fit.rpt

altera公司的FPGA的一些开发用的VHDL的源代码用于学习

; Router Timing Optimization Level                     ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                          ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                             ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                 ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                          ; Off                            ; Off                            ;
; Optimize Timing                                      ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing           ; On                             ; On                             ;
; Limit to One Fitting Attempt                         ; Off                            ; Off                            ;
; Final Placement Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations          ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                        ; 1                              ; 1                              ;
; Slow Slew Rate                                       ; Off                            ; Off                            ;
; PCI I/O                                              ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                            ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                   ; Off                            ; Off                            ;
; Auto Packed Registers -- Cyclone                     ; Auto                           ; Auto                           ;
; Auto Delay Chains                                    ; On                             ; On                             ;
; Auto Merge PLLs                                      ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic   ; Off                            ; Off                            ;
; Perform Register Duplication                         ; Off                            ; Off                            ;
; Perform Register Retiming                            ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining               ; Off                            ; Off                            ;
; Fitter Effort                                        ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                      ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication             ; Auto                           ; Auto                           ;
; Auto Register Duplication                            ; Off                            ; Off                            ;
; Auto Global Clock                                    ; On                             ; On                             ;
; Auto Global Register Control Signals                 ; On                             ; On                             ;
+------------------------------------------------------+--------------------------------+--------------------------------+


+--------------------------------------------------------------------+
; Fitter Device Options                                              ;
+----------------------------------------------+---------------------+
; Option                                       ; Setting             ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                 ;
; Enable device-wide reset (DEV_CLRn)          ; Off                 ;
; Enable device-wide output enable (DEV_OE)    ; Off                 ;
; Enable INIT_DONE output                      ; Off                 ;
; Configuration scheme                         ; Active Serial       ;
; Error detection CRC                          ; Off                 ;
; Reserve ASDO pin after configuration.        ; As input tri-stated ;
; Reserve all unused pins                      ; As input tri-stated ;
; Base pin-out file on sameframe device        ; Off                 ;
+----------------------------------------------+---------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in C:/pci/reg_wr/test.fit.eqn.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/pci/reg_wr/test.pin.


+-----------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                           ;
+---------------------------------------------+-------------------------------------------+
; Resource                                    ; Usage                                     ;
+---------------------------------------------+-------------------------------------------+
; Total logic elements                        ; 128 / 5,980 ( 2 % )                       ;
;     -- Combinational with no register       ; 15                                        ;
;     -- Register only                        ; 71                                        ;
;     -- Combinational with a register        ; 42                                        ;
;                                             ;                                           ;
; Logic element usage by number of LUT inputs ;                                           ;
;     -- 4 input functions                    ; 14                                        ;
;     -- 3 input functions                    ; 9                                         ;
;     -- 2 input functions                    ; 31                                        ;
;     -- 1 input functions                    ; 31                                        ;
;     -- 0 input functions                    ; 43                                        ;
;                                             ;                                           ;
; Logic elements by mode                      ;                                           ;
;     -- normal mode                          ; 101                                       ;
;     -- arithmetic mode                      ; 27                                        ;
;     -- qfbk mode                            ; 2                                         ;
;     -- register cascade mode                ; 0                                         ;
;     -- synchronous clear/load mode          ; 45                                        ;