test.tan.rpt

altera公司的FPGA的一些开发用的VHDL的源代码用于学习

+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; On                 ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                            ;
+-------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                           ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+-------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; pllll:inst3|altpll:altpll_component|_clk0 ;                    ; PLL output ; 30.0 MHz         ; 0.000 ns      ; 0.000 ns     ; SYSCLK   ; 3                     ; 5                   ; -1.885 ns ;              ;
; SYSCLK                                    ;                    ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+-------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'pllll:inst3|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                  ;
+-----------------------------------------+-----------------------------------------------------+-----------------------+-----------------------+-------------------------------------------+-------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                  ; To                    ; From Clock                                ; To Clock                                  ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------+-----------------------+-------------------------------------------+-------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 28.464 ns                               ; 205.38 MHz ( period = 4.869 ns )                    ; int:inst10|state.idle ; int:inst10|wr~reg0    ; pllll:inst3|altpll:altpll_component|_clk0 ; pllll:inst3|altpll:altpll_component|_clk0 ; 33.333 ns                   ; 33.072 ns                 ; 4.608 ns                ;
; 28.464 ns                               ; 205.38 MHz ( period = 4.869 ns )                    ; int:inst10|state.idle ; int:inst10|process0~7 ; pllll:inst3|altpll:altpll_component|_clk0 ; pllll:inst3|altpll:altpll_component|_clk0 ; 33.333 ns                   ; 33.072 ns                 ; 4.608 ns                ;
; 28.562 ns                               ; 209.60 MHz ( period = 4.771 ns )                    ; int:inst10|count[0]   ; int:inst10|state.w0   ; pllll:inst3|altpll:altpll_component|_clk0 ; pllll:inst3|altpll:altpll_component|_clk0 ; 33.333 ns                   ; 33.072 ns                 ; 4.510 ns                ;
; 28.566 ns                               ; 209.78 MHz ( period = 4.767 ns )                    ; int:inst10|state.w0   ; int:inst10|ccs~reg0   ; pllll:inst3|altpll:altpll_component|_clk0 ; pllll:inst3|altpll:altpll_component|_clk0 ; 33.333 ns                   ; 33.064 ns                 ; 4.498 ns                ;
; 28.566 ns                               ; 209.78 MHz ( period = 4.767 ns )                    ; int:inst10|state.w0   ; int:inst10|process0~0 ; pllll:inst3|altpll:altpll_component|_clk0 ; pllll:inst3|altpll:altpll_component|_clk0 ; 33.333 ns                   ; 33.064 ns                 ; 4.498 ns                ;
; 28.731 ns                               ; 217.30 MHz ( period = 4.602 ns )                    ; int:inst10|count[3]   ; int:inst10|state.w0   ; pllll:inst3|altpll:altpll_component|_clk0 ; pllll:inst3|altpll:altpll_component|_clk0 ; 33.333 ns                   ; 33.072 ns                 ; 4.341 ns                ;
; 28.806 ns                               ; 220.90 MHz ( period = 4.527 ns )                    ; int:inst10|count[0]   ; int:inst10|state.zz   ; pllll:inst3|altpll:altpll_component|_clk0 ; pllll:inst3|altpll:altpll_component|_clk0 ; 33.333 ns                   ; 33.072 ns                 ; 4.266 ns                ;
; 28.842 ns                               ; 222.67 MHz ( period = 4.491 ns )                    ; int:inst10|count[1]   ; int:inst10|state.w0   ; pllll:inst3|altpll:altpll_component|_clk0 ; pllll:inst3|altpll:altpll_component|_clk0 ; 33.333 ns                   ; 33.072 ns                 ; 4.230 ns                ;
; 28.857 ns                               ; 223.41 MHz ( period = 4.476 ns )                    ; int:inst10|state.r4   ; int:inst10|tempd1[9]  ; pllll:inst3|altpll:altpll_component|_clk0 ; pllll:inst3|altpll:altpll_component|_clk0 ; 33.333 ns                   ; 33.080 ns                 ; 4.223 ns                ;
; 28.857 ns                               ; 223.41 MHz ( period = 4.476 ns )                    ; int:inst10|state.r4   ; int:inst10|tempd1[7]  ; pllll:inst3|altpll:altpll_component|_clk0 ; pllll:inst3|altpll:altpll_component|_clk0 ; 33.333 ns                   ; 33.080 ns                 ; 4.223 ns                ;
; 28.857 ns                               ; 223.41 MHz ( period = 4.476 ns )                    ; int:inst10|state.r4   ; int:inst10|tempd1[6]  ; pllll:inst3|altpll:altpll_component|_clk0 ; pllll:inst3|altpll:altpll_component|_clk0 ; 33.333 ns                   ; 33.080 ns                 ; 4.223 ns                ;
; 28.857 ns                               ; 223.41 MHz ( period = 4.476 ns )                    ; int:inst10|state.r4   ; int:inst10|tempd1[5]  ; pllll:inst3|altpll:altpll_component|_clk0 ; pllll:inst3|altpll:altpll_component|_clk0 ; 33.333 ns                   ; 33.080 ns                 ; 4.223 ns                ;