test.tan.rpt

altera公司的FPGA的一些开发用的VHDL的源代码用于学习

Timing Analyzer report for test
Fri Oct 20 19:02:09 2006
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'pllll:inst3|altpll:altpll_component|_clk0'
  6. Clock Hold: 'pllll:inst3|altpll:altpll_component|_clk0'
  7. tsu
  8. tco
  9. th
 10. Minimum tco
 11. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                              ;
+----------------------------------------------------------+-----------+----------------------------------+----------------------------------+-------------------------------------------+----------------------+-------------------------------------------+-------------------------------------------+--------------+
; Type                                                     ; Slack     ; Required Time                    ; Actual Time                      ; From                                      ; To                   ; From Clock                                ; To Clock                                  ; Failed Paths ;
+----------------------------------------------------------+-----------+----------------------------------+----------------------------------+-------------------------------------------+----------------------+-------------------------------------------+-------------------------------------------+--------------+
; Worst-case tsu                                           ; N/A       ; None                             ; 12.197 ns                        ; LRESETo_                                  ; int:inst10|t_dout[4] ; --                                        ; SYSCLK                                    ; 0            ;
; Worst-case tco                                           ; N/A       ; None                             ; 9.008 ns                         ; int:inst10|process0~7                     ; LW/R_                ; SYSCLK                                    ; --                                        ; 0            ;
; Worst-case th                                            ; N/A       ; None                             ; -6.078 ns                        ; LD[7]                                     ; int:inst10|tempd1[7] ; --                                        ; SYSCLK                                    ; 0            ;
; Worst-case Minimum tco                                   ; N/A       ; None                             ; 2.803 ns                         ; pllll:inst3|altpll:altpll_component|_clk0 ; LCLK                 ; SYSCLK                                    ; --                                        ; 0            ;
; Clock Setup: 'pllll:inst3|altpll:altpll_component|_clk0' ; 28.464 ns ; 30.00 MHz ( period = 33.333 ns ) ; 205.38 MHz ( period = 4.869 ns ) ; int:inst10|state.idle                     ; int:inst10|wr~reg0   ; pllll:inst3|altpll:altpll_component|_clk0 ; pllll:inst3|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'pllll:inst3|altpll:altpll_component|_clk0'  ; 0.860 ns  ; 30.00 MHz ( period = 33.333 ns ) ; N/A                              ; int:inst10|tempd1[1]                      ; int:inst10|t_dout[1] ; pllll:inst3|altpll:altpll_component|_clk0 ; pllll:inst3|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                             ;           ;                                  ;                                  ;                                           ;                      ;                                           ;                                           ; 0            ;
+----------------------------------------------------------+-----------+----------------------------------+----------------------------------+-------------------------------------------+----------------------+-------------------------------------------+-------------------------------------------+--------------+