test.vhd

altera公司的FPGA的一些开发用的VHDL的源代码用于学习

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 6.0 Build 178 04/27/2006 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY test IS 
	port
	(
		SYSCLK :  IN  STD_LOGIC;
		LRESETo_ :  IN  STD_LOGIC;
		pin_name :  IN  STD_LOGIC;
		LINT :  INOUT  STD_LOGIC;
		LA :  INOUT  STD_LOGIC_VECTOR(31 downto 2);
		LBE :  INOUT  STD_LOGIC_VECTOR(3 downto 0);
		LD :  INOUT  STD_LOGIC_VECTOR(31 downto 0);
		TEST :  OUT  STD_LOGIC;
		LCLK :  OUT  STD_LOGIC;
		LW/R_ :  OUT  STD_LOGIC;
		BLAST_ :  OUT  STD_LOGIC;
		ADS_ :  OUT  STD_LOGIC;
		CCS_ :  OUT  STD_LOGIC;
		DDDD :  OUT  STD_LOGIC_VECTOR(27 downto 0)
	);
END test;

ARCHITECTURE bdf_type OF test IS 

attribute black_box : boolean;
attribute noopt : boolean;

component interrupt
	PORT(LINT : IN STD_LOGIC;
		 READY : IN STD_LOGIC;
		 LCLK : IN STD_LOGIC;
		 RST : IN STD_LOGIC;
		 LD : INOUT STD_LOGIC_VECTOR(31 downto 0);
		 CCS : OUT STD_LOGIC;
		 ADS : OUT STD_LOGIC;
		 BLAST : OUT STD_LOGIC;
		 WR : OUT STD_LOGIC;
		 LINT1 : OUT STD_LOGIC;
		 LINT2 : OUT STD_LOGIC;
		 CTL : OUT STD_LOGIC;
		 COUNT1 : OUT STD_LOGIC_VECTOR(27 downto 0);
		 LA : OUT STD_LOGIC_VECTOR(31 downto 2);
		 LBE : OUT STD_LOGIC_VECTOR(3 downto 0)
	);
end component;

component ttri
	PORT(enabledt : IN STD_LOGIC;
		 data : IN STD_LOGIC;
		 enabletr : IN STD_LOGIC;
		 tridata : INOUT STD_LOGIC_VECTOR(0 to 0);
		 result : OUT STD_LOGIC
	);
end component;

signal	CTL :  STD_LOGIC;
signal	INT :  STD_LOGIC;
signal	INTO :  STD_LOGIC;
signal	RST :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_0 :  STD_LOGIC;


BEGIN 
TEST <= '0';
LCLK <= SYSCLK;



b2v_inst2 : interrupt
PORT MAP(LINT => INTO,
		 LCLK => SYSCLK,
		 RST => RST,
		 LD => LD,
		 CCS => CCS_,
		 ADS => ADS_,
		 BLAST => BLAST_,
		 WR => LW/R_,
		 CTL => CTL,
		 LA => LA);

b2v_inst3 : ttri
PORT MAP(enabledt => SYNTHESIZED_WIRE_0,
		 data => INTO,
		 enabletr => CTL,
		 tridata(0) => LINT);

SYNTHESIZED_WIRE_0 <= NOT(CTL);

INTO <= pin_name;
RST <= LRESETo_;

END;