test.tan.summary

altera公司的FPGA的一些开发用的VHDL的源代码用于学习

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 12.197 ns
From           : LRESETo_
To             : int:inst10|t_dout[4]
From Clock     : --
To Clock       : SYSCLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 9.008 ns
From           : int:inst10|process0~7
To             : LW/R_
From Clock     : SYSCLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -6.078 ns
From           : LD[7]
To             : int:inst10|tempd1[7]
From Clock     : --
To Clock       : SYSCLK
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 2.803 ns
From           : pllll:inst3|altpll:altpll_component|_clk0
To             : LCLK
From Clock     : SYSCLK
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'pllll:inst3|altpll:altpll_component|_clk0'
Slack          : 28.464 ns
Required Time  : 30.00 MHz ( period = 33.333 ns )
Actual Time    : 205.38 MHz ( period = 4.869 ns )
From           : int:inst10|state.idle
To             : int:inst10|wr~reg0
From Clock     : pllll:inst3|altpll:altpll_component|_clk0
To Clock       : pllll:inst3|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'pllll:inst3|altpll:altpll_component|_clk0'
Slack          : 0.860 ns
Required Time  : 30.00 MHz ( period = 33.333 ns )
Actual Time    : N/A
From           : int:inst10|tempd1[1]
To             : int:inst10|t_dout[1]
From Clock     : pllll:inst3|altpll:altpll_component|_clk0
To Clock       : pllll:inst3|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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