dds.fit.summary

dds实现波形的生成

Flow Status : Successful - Wed Jul 26 13:34:25 2006
Quartus II Version : 5.0 Build 171 11/03/2005 SP 2 SJ Full Version
Revision Name : DDS
Top-level Entity Name : DDS_VHDL
Family : Stratix GX
Device : EP1SGX40GF1020C5
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 20 / 41,250 ( < 1 % )
Total pins : 21 / 639 ( 3 % )
Total virtual pins : 0
Total memory bits : 10,240 / 3,423,744 ( < 1 % )
DSP block 9-bit elements : 0 / 112 ( 0 % )
Total PLLs : 0 / 13 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )