dds.tan.qmsg

dds实现波形的生成

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "CLK FOUT\[7\] lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\|q_a\[7\] 7.510 ns memory " "Info: Minimum tco from clock \"CLK\" to destination pin \"FOUT\[7\]\" through memory \"lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\|q_a\[7\]\" is 7.510 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.476 ns + Shortest memory " "Info: + Shortest clock path from clock \"CLK\" to source memory is 3.476 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.880 ns) 0.880 ns CLK 1 CLK PIN_D16 60 " "Info: 1: + IC(0.000 ns) + CELL(0.880 ns) = 0.880 ns; Loc. = PIN_D16; Fanout = 60; CLK Node = 'CLK'" {  } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { CLK } "NODE_NAME" } "" } } { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.096 ns) + CELL(0.500 ns) 3.476 ns lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\|q_a\[7\] 2 MEM M4K_X39_Y56 1 " "Info: 2: + IC(2.096 ns) + CELL(0.500 ns) = 3.476 ns; Loc. = M4K_X39_Y56; Fanout = 1; MEM Node = 'lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\|q_a\[7\]'" {  } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "2.596 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[7] } "NODE_NAME" } "" } } { "db/altsyncram_obq.tdf" "" { Text "D:/cwdds/db/altsyncram_obq.tdf" 38 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.380 ns 39.70 % " "Info: Total cell delay = 1.380 ns ( 39.70 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.096 ns 60.30 % " "Info: Total interconnect delay = 2.096 ns ( 60.30 % )" {  } {  } 0}  } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "3.476 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[7] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.476 ns" { CLK CLK~out0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[7] } { 0.0ns 0.0ns 2.096ns } { 0.0ns 0.88ns 0.5ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.420 ns + " "Info: + Micro clock to output delay of source is 0.420 ns" {  } { { "db/altsyncram_obq.tdf" "" { Text "D:/cwdds/db/altsyncram_obq.tdf" 38 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.614 ns + Shortest memory pin " "Info: + Shortest memory to pin delay is 3.614 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.071 ns lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\|q_a\[7\] 1 MEM M4K_X39_Y56 1 " "Info: 1: + IC(0.000 ns) + CELL(0.071 ns) = 0.071 ns; Loc. = M4K_X39_Y56; Fanout = 1; MEM Node = 'lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\|q_a\[7\]'" {  } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[7] } "NODE_NAME" } "" } } { "db/altsyncram_obq.tdf" "" { Text "D:/cwdds/db/altsyncram_obq.tdf" 38 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.139 ns) + CELL(2.404 ns) 3.614 ns FOUT\[7\] 2 PIN PIN_G20 0 " "Info: 2: + IC(1.139 ns) + CELL(2.404 ns) = 3.614 ns; Loc. = PIN_G20; Fanout = 0; PIN Node = 'FOUT\[7\]'" {  } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "3.543 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[7] FOUT[7] } "NODE_NAME" } "" } } { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.475 ns 68.48 % " "Info: Total cell delay = 2.475 ns ( 68.48 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.139 ns 31.52 % " "Info: Total interconnect delay = 1.139 ns ( 31.52 % )" {  } {  } 0}  } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "3.614 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[7] FOUT[7] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.614 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[7] FOUT[7] } { 0.0ns 1.139ns } { 0.071ns 2.404ns } } }  } 0}  } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "3.476 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[7] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.476 ns" { CLK CLK~out0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[7] } { 0.0ns 0.0ns 2.096ns } { 0.0ns 0.88ns 0.5ns } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "3.614 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[7] FOUT[7] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.614 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[7] FOUT[7] } { 0.0ns 1.139ns } { 0.071ns 2.404ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 26 13:34:51 2006 " "Info: Processing ended: Wed Jul 26 13:34:51 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}