📄 dds.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK memory lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\|ram_block1a3~porta_address_reg0 memory lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\|q_a\[6\] 290.87 MHz 3.438 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 290.87 MHz between source memory \"lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\|ram_block1a3~porta_address_reg0\" and destination memory \"lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\|q_a\[6\]\" (period= 3.438 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.875 ns + Longest memory memory " "Info: + Longest memory to memory delay is 2.875 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\|ram_block1a3~porta_address_reg0 1 MEM M4K_X39_Y57 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X39_Y57; Fanout = 2; MEM Node = 'lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\|ram_block1a3~porta_address_reg0'" { } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a3~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_obq.tdf" "" { Text "D:/cwdds/db/altsyncram_obq.tdf" 98 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.875 ns) 2.875 ns lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\|q_a\[6\] 2 MEM M4K_X39_Y57 1 " "Info: 2: + IC(0.000 ns) + CELL(2.875 ns) = 2.875 ns; Loc. = M4K_X39_Y57; Fanout = 1; MEM Node = 'lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\|q_a\[6\]'" { } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "2.875 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a3~porta_address_reg0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[6] } "NODE_NAME" } "" } } { "db/altsyncram_obq.tdf" "" { Text "D:/cwdds/db/altsyncram_obq.tdf" 38 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.875 ns 100.00 % " "Info: Total cell delay = 2.875 ns ( 100.00 % )" { } { } 0} } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "2.875 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a3~porta_address_reg0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[6] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.875 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a3~porta_address_reg0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[6] } { 0.000ns 0.000ns } { 0.000ns 2.875ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.012 ns - Smallest " "Info: - Smallest clock skew is -0.012 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.482 ns + Shortest memory " "Info: + Shortest clock path from clock \"CLK\" to destination memory is 3.482 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.880 ns) 0.880 ns CLK 1 CLK PIN_D16 60 " "Info: 1: + IC(0.000 ns) + CELL(0.880 ns) = 0.880 ns; Loc. = PIN_D16; Fanout = 60; CLK Node = 'CLK'" { } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { CLK } "NODE_NAME" } "" } } { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.102 ns) + CELL(0.500 ns) 3.482 ns lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\|q_a\[6\] 2 MEM M4K_X39_Y57 1 " "Info: 2: + IC(2.102 ns) + CELL(0.500 ns) = 3.482 ns; Loc. = M4K_X39_Y57; Fanout = 1; MEM Node = 'lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\|q_a\[6\]'" { } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "2.602 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[6] } "NODE_NAME" } "" } } { "db/altsyncram_obq.tdf" "" { Text "D:/cwdds/db/altsyncram_obq.tdf" 38 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.380 ns 39.63 % " "Info: Total cell delay = 1.380 ns ( 39.63 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.102 ns 60.37 % " "Info: Total interconnect delay = 2.102 ns ( 60.37 % )" { } { } 0} } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "3.482 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[6] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.482 ns" { CLK CLK~out0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[6] } { 0.000ns 0.000ns 2.102ns } { 0.000ns 0.880ns 0.500ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.494 ns - Longest memory " "Info: - Longest clock path from clock \"CLK\" to source memory is 3.494 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.880 ns) 0.880 ns CLK 1 CLK PIN_D16 60 " "Info: 1: + IC(0.000 ns) + CELL(0.880 ns) = 0.880 ns; Loc. = PIN_D16; Fanout = 60; CLK Node = 'CLK'" { } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { CLK } "NODE_NAME" } "" } } { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.102 ns) + CELL(0.512 ns) 3.494 ns lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\|ram_block1a3~porta_address_reg0 2 MEM M4K_X39_Y57 2 " "Info: 2: + IC(2.102 ns) + CELL(0.512 ns) = 3.494 ns; Loc. = M4K_X39_Y57; Fanout = 2; MEM Node = 'lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\|ram_block1a3~porta_address_reg0'" { } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "2.614 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a3~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_obq.tdf" "" { Text "D:/cwdds/db/altsyncram_obq.tdf" 98 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.392 ns 39.84 % " "Info: Total cell delay = 1.392 ns ( 39.84 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.102 ns 60.16 % " "Info: Total interconnect delay = 2.102 ns ( 60.16 % )" { } { } 0} } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "3.494 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a3~porta_address_reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.494 ns" { CLK CLK~out0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a3~porta_address_reg0 } { 0.000ns 0.000ns 2.102ns } { 0.000ns 0.880ns 0.512ns } } } } 0} } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "3.482 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[6] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.482 ns" { CLK CLK~out0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[6] } { 0.000ns 0.000ns 2.102ns } { 0.000ns 0.880ns 0.500ns } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "3.494 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a3~porta_address_reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.494 ns" { CLK CLK~out0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a3~porta_address_reg0 } { 0.000ns 0.000ns 2.102ns } { 0.000ns 0.880ns 0.512ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.420 ns + " "Info: + Micro clock to output delay of source is 0.420 ns" { } { { "db/altsyncram_obq.tdf" "" { Text "D:/cwdds/db/altsyncram_obq.tdf" 98 2 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.131 ns + " "Info: + Micro setup delay of destination is 0.131 ns" { } { { "db/altsyncram_obq.tdf" "" { Text "D:/cwdds/db/altsyncram_obq.tdf" 38 2 0 } } } 0} } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "2.875 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a3~porta_address_reg0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[6] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.875 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a3~porta_address_reg0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[6] } { 0.000ns 0.000ns } { 0.000ns 2.875ns } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "3.482 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[6] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.482 ns" { CLK CLK~out0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[6] } { 0.000ns 0.000ns 2.102ns } { 0.000ns 0.880ns 0.500ns } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "3.494 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a3~porta_address_reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.494 ns" { CLK CLK~out0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a3~porta_address_reg0 } { 0.000ns 0.000ns 2.102ns } { 0.000ns 0.880ns 0.512ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "REG10B:u2\|DOUT\[5\] FWORD\[0\] CLK 4.063 ns register " "Info: tsu for register \"REG10B:u2\|DOUT\[5\]\" (data pin = \"FWORD\[0\]\", clock pin = \"CLK\") is 4.063 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.583 ns + Longest pin register " "Info: + Longest pin to register delay is 7.583 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns FWORD\[0\] 1 PIN PIN_C17 3 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_C17; Fanout = 3; PIN Node = 'FWORD\[0\]'" { } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { FWORD[0] } "NODE_NAME" } "" } } { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.169 ns) + CELL(0.451 ns) 6.707 ns REG10B:u2\|DOUT\[0\]~71COUT1_111 2 COMB LC_X42_Y58_N0 2 " "Info: 2: + IC(5.169 ns) + CELL(0.451 ns) = 6.707 ns; Loc. = LC_X42_Y58_N0; Fanout = 2; COMB Node = 'REG10B:u2\|DOUT\[0\]~71COUT1_111'" { } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "5.620 ns" { FWORD[0] REG10B:u2|DOUT[0]~71COUT1_111 } "NODE_NAME" } "" } } { "REG10B.VHD" "" { Text "D:/cwdds/REG10B.VHD" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 6.767 ns REG10B:u2\|DOUT\[1\]~75COUT1_112 3 COMB LC_X42_Y58_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.060 ns) = 6.767 ns; Loc. = LC_X42_Y58_N1; Fanout = 2; COMB Node = 'REG10B:u2\|DOUT\[1\]~75COUT1_112'" { } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "0.060 ns" { REG10B:u2|DOUT[0]~71COUT1_111 REG10B:u2|DOUT[1]~75COUT1_112 } "NODE_NAME" } "" } } { "REG10B.VHD" "" { Text "D:/cwdds/REG10B.VHD" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 6.827 ns REG10B:u2\|DOUT\[2\]~79COUT1_113 4 COMB LC_X42_Y58_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.060 ns) = 6.827 ns; Loc. = LC_X42_Y58_N2; Fanout = 2; COMB Node = 'REG10B:u2\|DOUT\[2\]~79COUT1_113'" { } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "0.060 ns" { REG10B:u2|DOUT[1]~75COUT1_112 REG10B:u2|DOUT[2]~79COUT1_113 } "NODE_NAME" } "" } } { "REG10B.VHD" "" { Text "D:/cwdds/REG10B.VHD" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 6.887 ns REG10B:u2\|DOUT\[3\]~83COUT1_114 5 COMB LC_X42_Y58_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 6.887 ns; Loc. = LC_X42_Y58_N3; Fanout = 2; COMB Node = 'REG10B:u2\|DOUT\[3\]~83COUT1_114'" { } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "0.060 ns" { REG10B:u2|DOUT[2]~79COUT1_113 REG10B:u2|DOUT[3]~83COUT1_114 } "NODE_NAME" } "" } } { "REG10B.VHD" "" { Text "D:/cwdds/REG10B.VHD" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.118 ns) 7.005 ns REG10B:u2\|DOUT\[4\]~87 6 COMB LC_X42_Y58_N4 5 " "Info: 6: + IC(0.000 ns) + CELL(0.118 ns) = 7.005 ns; Loc. = LC_X42_Y58_N4; Fanout = 5; COMB Node = 'REG10B:u2\|DOUT\[4\]~87'" { } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "0.118 ns" { REG10B:u2|DOUT[3]~83COUT1_114 REG10B:u2|DOUT[4]~87 } "NODE_NAME" } "" } } { "REG10B.VHD" "" { Text "D:/cwdds/REG10B.VHD" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.578 ns) 7.583 ns REG10B:u2\|DOUT\[5\] 7 REG LC_X42_Y58_N5 4 " "Info: 7: + IC(0.000 ns) + CELL(0.578 ns) = 7.583 ns; Loc. = LC_X42_Y58_N5; Fanout = 4; REG Node = 'REG10B:u2\|DOUT\[5\]'" { } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "0.578 ns" { REG10B:u2|DOUT[4]~87 REG10B:u2|DOUT[5] } "NODE_NAME" } "" } } { "REG10B.VHD" "" { Text "D:/cwdds/REG10B.VHD" 6 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.414 ns 31.83 % " "Info: Total cell delay = 2.414 ns ( 31.83 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.169 ns 68.17 % " "Info: Total interconnect delay = 5.169 ns ( 68.17 % )" { } { } 0} } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "7.583 ns" { FWORD[0] REG10B:u2|DOUT[0]~71COUT1_111 REG10B:u2|DOUT[1]~75COUT1_112 REG10B:u2|DOUT[2]~79COUT1_113 REG10B:u2|DOUT[3]~83COUT1_114 REG10B:u2|DOUT[4]~87 REG10B:u2|DOUT[5] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "7.583 ns" { FWORD[0] FWORD[0]~out0 REG10B:u2|DOUT[0]~71COUT1_111 REG10B:u2|DOUT[1]~75COUT1_112 REG10B:u2|DOUT[2]~79COUT1_113 REG10B:u2|DOUT[3]~83COUT1_114 REG10B:u2|DOUT[4]~87 REG10B:u2|DOUT[5] } { 0.000ns 0.000ns 5.169ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.087ns 0.451ns 0.060ns 0.060ns 0.060ns 0.118ns 0.578ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "REG10B.VHD" "" { Text "D:/cwdds/REG10B.VHD" 6 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.530 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 3.530 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.880 ns) 0.880 ns CLK 1 CLK PIN_D16 60 " "Info: 1: + IC(0.000 ns) + CELL(0.880 ns) = 0.880 ns; Loc. = PIN_D16; Fanout = 60; CLK Node = 'CLK'" { } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { CLK } "NODE_NAME" } "" } } { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.108 ns) + CELL(0.542 ns) 3.530 ns REG10B:u2\|DOUT\[5\] 2 REG LC_X42_Y58_N5 4 " "Info: 2: + IC(2.108 ns) + CELL(0.542 ns) = 3.530 ns; Loc. = LC_X42_Y58_N5; Fanout = 4; REG Node = 'REG10B:u2\|DOUT\[5\]'" { } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "2.650 ns" { CLK REG10B:u2|DOUT[5] } "NODE_NAME" } "" } } { "REG10B.VHD" "" { Text "D:/cwdds/REG10B.VHD" 6 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.422 ns 40.28 % " "Info: Total cell delay = 1.422 ns ( 40.28 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.108 ns 59.72 % " "Info: Total interconnect delay = 2.108 ns ( 59.72 % )" { } { } 0} } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "3.530 ns" { CLK REG10B:u2|DOUT[5] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.530 ns" { CLK CLK~out0 REG10B:u2|DOUT[5] } { 0.000ns 0.000ns 2.108ns } { 0.000ns 0.880ns 0.542ns } } } } 0} } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "7.583 ns" { FWORD[0] REG10B:u2|DOUT[0]~71COUT1_111 REG10B:u2|DOUT[1]~75COUT1_112 REG10B:u2|DOUT[2]~79COUT1_113 REG10B:u2|DOUT[3]~83COUT1_114 REG10B:u2|DOUT[4]~87 REG10B:u2|DOUT[5] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "7.583 ns" { FWORD[0] FWORD[0]~out0 REG10B:u2|DOUT[0]~71COUT1_111 REG10B:u2|DOUT[1]~75COUT1_112 REG10B:u2|DOUT[2]~79COUT1_113 REG10B:u2|DOUT[3]~83COUT1_114 REG10B:u2|DOUT[4]~87 REG10B:u2|DOUT[5] } { 0.000ns 0.000ns 5.169ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.087ns 0.451ns 0.060ns 0.060ns 0.060ns 0.118ns 0.578ns } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "3.530 ns" { CLK REG10B:u2|DOUT[5] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.530 ns" { CLK CLK~out0 REG10B:u2|DOUT[5] } { 0.000ns 0.000ns 2.108ns } { 0.000ns 0.880ns 0.542ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK FOUT\[8\] lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\|q_a\[8\] 8.049 ns memory " "Info: tco from clock \"CLK\" to destination pin \"FOUT\[8\]\" through memory \"lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\|q_a\[8\]\" is 8.049 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.470 ns + Longest memory " "Info: + Longest clock path from clock \"CLK\" to source memory is 3.470 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.880 ns) 0.880 ns CLK 1 CLK PIN_D16 60 " "Info: 1: + IC(0.000 ns) + CELL(0.880 ns) = 0.880 ns; Loc. = PIN_D16; Fanout = 60; CLK Node = 'CLK'" { } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { CLK } "NODE_NAME" } "" } } { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.090 ns) + CELL(0.500 ns) 3.470 ns lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\|q_a\[8\] 2 MEM M4K_X39_Y55 1 " "Info: 2: + IC(2.090 ns) + CELL(0.500 ns) = 3.470 ns; Loc. = M4K_X39_Y55; Fanout = 1; MEM Node = 'lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\|q_a\[8\]'" { } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "2.590 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[8] } "NODE_NAME" } "" } } { "db/altsyncram_obq.tdf" "" { Text "D:/cwdds/db/altsyncram_obq.tdf" 38 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.380 ns 39.77 % " "Info: Total cell delay = 1.380 ns ( 39.77 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.090 ns 60.23 % " "Info: Total interconnect delay = 2.090 ns ( 60.23 % )" { } { } 0} } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "3.470 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[8] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.470 ns" { CLK CLK~out0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[8] } { 0.000ns 0.000ns 2.090ns } { 0.000ns 0.880ns 0.500ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.420 ns + " "Info: + Micro clock to output delay of source is 0.420 ns" { } { { "db/altsyncram_obq.tdf" "" { Text "D:/cwdds/db/altsyncram_obq.tdf" 38 2 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.159 ns + Longest memory pin " "Info: + Longest memory to pin delay is 4.159 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.071 ns lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\|q_a\[8\] 1 MEM M4K_X39_Y55 1 " "Info: 1: + IC(0.000 ns) + CELL(0.071 ns) = 0.071 ns; Loc. = M4K_X39_Y55; Fanout = 1; MEM Node = 'lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\|q_a\[8\]'" { } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[8] } "NODE_NAME" } "" } } { "db/altsyncram_obq.tdf" "" { Text "D:/cwdds/db/altsyncram_obq.tdf" 38 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.401 ns) + CELL(2.687 ns) 4.159 ns FOUT\[8\] 2 PIN PIN_D18 0 " "Info: 2: + IC(1.401 ns) + CELL(2.687 ns) = 4.159 ns; Loc. = PIN_D18; Fanout = 0; PIN Node = 'FOUT\[8\]'" { } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "4.088 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[8] FOUT[8] } "NODE_NAME" } "" } } { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.758 ns 66.31 % " "Info: Total cell delay = 2.758 ns ( 66.31 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.401 ns 33.69 % " "Info: Total interconnect delay = 1.401 ns ( 33.69 % )" { } { } 0} } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "4.159 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[8] FOUT[8] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "4.159 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[8] FOUT[8] } { 0.000ns 1.401ns } { 0.071ns 2.687ns } } } } 0} } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "3.470 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[8] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.470 ns" { CLK CLK~out0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[8] } { 0.000ns 0.000ns 2.090ns } { 0.000ns 0.880ns 0.500ns } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "4.159 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[8] FOUT[8] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "4.159 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[8] FOUT[8] } { 0.000ns 1.401ns } { 0.071ns 2.687ns } } } } 0}
{ "Info" "ITDB_TH_RESULT" "REG10B:u2\|DOUT\[1\] FWORD\[1\] CLK -2.727 ns register " "Info: th for register \"REG10B:u2\|DOUT\[1\]\" (data pin = \"FWORD\[1\]\", clock pin = \"CLK\") is -2.727 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.530 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 3.530 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.880 ns) 0.880 ns CLK 1 CLK PIN_D16 60 " "Info: 1: + IC(0.000 ns) + CELL(0.880 ns) = 0.880 ns; Loc. = PIN_D16; Fanout = 60; CLK Node = 'CLK'" { } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { CLK } "NODE_NAME" } "" } } { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.108 ns) + CELL(0.542 ns) 3.530 ns REG10B:u2\|DOUT\[1\] 2 REG LC_X42_Y58_N1 4 " "Info: 2: + IC(2.108 ns) + CELL(0.542 ns) = 3.530 ns; Loc. = LC_X42_Y58_N1; Fanout = 4; REG Node = 'REG10B:u2\|DOUT\[1\]'" { } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "2.650 ns" { CLK REG10B:u2|DOUT[1] } "NODE_NAME" } "" } } { "REG10B.VHD" "" { Text "D:/cwdds/REG10B.VHD" 6 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.422 ns 40.28 % " "Info: Total cell delay = 1.422 ns ( 40.28 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.108 ns 59.72 % " "Info: Total interconnect delay = 2.108 ns ( 59.72 % )" { } { } 0} } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "3.530 ns" { CLK REG10B:u2|DOUT[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.530 ns" { CLK CLK~out0 REG10B:u2|DOUT[1] } { 0.000ns 0.000ns 2.108ns } { 0.000ns 0.880ns 0.542ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "REG10B.VHD" "" { Text "D:/cwdds/REG10B.VHD" 6 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.357 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.357 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.880 ns) 0.880 ns FWORD\[1\] 1 PIN PIN_C19 3 " "Info: 1: + IC(0.000 ns) + CELL(0.880 ns) = 0.880 ns; Loc. = PIN_C19; Fanout = 3; PIN Node = 'FWORD\[1\]'" { } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { FWORD[1] } "NODE_NAME" } "" } } { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.938 ns) + CELL(0.539 ns) 6.357 ns REG10B:u2\|DOUT\[1\] 2 REG LC_X42_Y58_N1 4 " "Info: 2: + IC(4.938 ns) + CELL(0.539 ns) = 6.357 ns; Loc. = LC_X42_Y58_N1; Fanout = 4; REG Node = 'REG10B:u2\|DOUT\[1\]'" { } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "5.477 ns" { FWORD[1] REG10B:u2|DOUT[1] } "NODE_NAME" } "" } } { "REG10B.VHD" "" { Text "D:/cwdds/REG10B.VHD" 6 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.419 ns 22.32 % " "Info: Total cell delay = 1.419 ns ( 22.32 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.938 ns 77.68 % " "Info: Total interconnect delay = 4.938 ns ( 77.68 % )" { } { } 0} } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "6.357 ns" { FWORD[1] REG10B:u2|DOUT[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.357 ns" { FWORD[1] FWORD[1]~out0 REG10B:u2|DOUT[1] } { 0.000ns 0.000ns 4.938ns } { 0.000ns 0.880ns 0.539ns } } } } 0} } { { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "3.530 ns" { CLK REG10B:u2|DOUT[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.530 ns" { CLK CLK~out0 REG10B:u2|DOUT[1] } { 0.000ns 0.000ns 2.108ns } { 0.000ns 0.880ns 0.542ns } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "6.357 ns" { FWORD[1] REG10B:u2|DOUT[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.357 ns" { FWORD[1] FWORD[1]~out0 REG10B:u2|DOUT[1] } { 0.000ns 0.000ns 4.938ns } { 0.000ns 0.880ns 0.539ns } } } } 0}
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