dds.hif

dds实现波形的生成

Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
9
681
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
DDS_VHDL
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
DDS_VHDL.vhd
1148988950
4
# storage
db|DDS.(0).cnf
db|DDS.(0).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
|
}
# end
# entity
ADDER10B
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
ADDER10B.VHD
1089432724
4
# storage
db|DDS.(1).cnf
db|DDS.(1).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
ADDER10B:u1
}
# end
# entity
REG10B
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
REG10B.VHD
1089432902
4
# storage
db|DDS.(2).cnf
db|DDS.(2).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
REG10B:u2
REG10B:u3
}
# end
# entity
lpm_rom0
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
lpm_rom0.vhd
1148893004
4
# storage
db|DDS.(3).cnf
db|DDS.(3).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
lpm_rom0:u6
}
# end
# entity
altsyncram
# case_insensitive
# source_file
e:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|DDS.(4).cnf
db|DDS.(4).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
10
PARAMETER_DEC
USR
WIDTHAD_A
10
PARAMETER_DEC
USR
NUMWORDS_A
1024
PARAMETER_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
sinsin.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix GX
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_obq
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
}
# include_file {
e:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
e:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
e:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
e:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1131033050
e:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
e:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
e:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
e:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
e:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
e:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
}
# hierarchies {
lpm_rom0:u6|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_obq
# case_insensitive
# source_file
db|altsyncram_obq.tdf
1153892026
6
# storage
db|DDS.(5).cnf
db|DDS.(5).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
}
# memory_file {
sinsin.mif
1148904388
}
# hierarchies {
lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated
}
# end
# complete