dds.qsf

dds实现波形的生成

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		DDS_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:53:16  JUNE 11, 2006"
set_global_assignment -name LAST_QUARTUS_VERSION "5.0 SP2"
set_global_assignment -name VHDL_FILE REG10B.VHD
set_global_assignment -name VHDL_FILE lpm_rom0.vhd
set_global_assignment -name VHDL_FILE DDS_VHDL.vhd
set_global_assignment -name VHDL_FILE ADDER10B.VHD

# Timing Assignments
# ==================
set_global_assignment -name DO_MIN_ANALYSIS ON
set_global_assignment -name IGNORE_CLOCK_SETTINGS ON

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
set_global_assignment -name FAMILY "Stratix GX"
set_global_assignment -name TOP_LEVEL_ENTITY DDS_VHDL

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1SGX40GF1020C5
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"

# Simulator Assignments
# =====================
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name VECTOR_INPUT_SOURCE dds_vhdl.vwf

# ---------------------------------------
# start EDA_TOOL_SETTINGS(eda_simulation)

	# EDA Netlist Writer Assignments
	# ==============================
	set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation
	set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulation
	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation

# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------