dds_vhd.sdo

dds实现波形的生成

    (CELLTYPE "stratixgx_lcell_register")
    (INSTANCE u2_aDOUT_a9_a_aI.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2650:2650:2650) (2627:2627:2627))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratixgx_asynch_lcell")
    (INSTANCE u3_aDOUT_a9_a_aI.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (958:958:958) (919:919:919))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixgx_lcell_register")
    (INSTANCE u3_aDOUT_a9_a_aI.lereg)
    (DELAY
      (ABSOLUTE
        (PORT datac (1043:1043:1043) (1004:1004:1004))
        (PORT aclr (645:645:645) (645:645:645))
        (PORT clk (2653:2653:2653) (2631:2631:2631))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datac (posedge clk) (10:10:10))
      (HOLD datac (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratixgx_ram_register")
    (INSTANCE u6_aaltsyncram_component_aauto_generated_aram_block1a0.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (2608:2608:2608) (2586:2586:2586))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (131:131:131))
      (HOLD d (posedge clk) (34:34:34))
    )
  )
  (CELL
    (CELLTYPE "stratixgx_ram_register")
    (INSTANCE u6_aaltsyncram_component_aauto_generated_aram_block1a0.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1308:1308:1308) (1299:1299:1299))
        (PORT d[1] (1227:1227:1227) (1175:1175:1175))
        (PORT d[2] (1203:1203:1203) (1166:1166:1166))
        (PORT d[3] (1248:1248:1248) (1186:1186:1186))
        (PORT d[4] (1309:1309:1309) (1301:1301:1301))
        (PORT d[5] (1593:1593:1593) (1562:1562:1562))
        (PORT d[6] (1334:1334:1334) (1328:1328:1328))
        (PORT d[7] (1588:1588:1588) (1556:1556:1556))
        (PORT d[8] (1588:1588:1588) (1566:1566:1566))
        (PORT d[9] (1333:1333:1333) (1329:1329:1329))
        (PORT clk (2608:2608:2608) (2586:2586:2586))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (131:131:131))
      (HOLD d (posedge clk) (34:34:34))
    )
  )
  (CELL
    (CELLTYPE "stratixgx_ram_register")
    (INSTANCE u6_aaltsyncram_component_aauto_generated_aram_block1a0.active_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (2608:2608:2608) (2608:2608:2608))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixgx_ram_pulse_generator")
    (INSTANCE u6_aaltsyncram_component_aauto_generated_aram_block1a0.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (3028:3028:3028) (3006:3006:3006))
        (IOPATH (posedge clk) pulse (0:0:0) (1943:1943:1943))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixgx_ram_register")
    (INSTANCE u6_aaltsyncram_component_aauto_generated_aram_block1a0.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (2596:2596:2596) (2574:2574:2574))
        (IOPATH (posedge clk) q (491:491:491) (491:491:491))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (131:131:131))
      (HOLD d (posedge clk) (34:34:34))
    )
  )
  (CELL
    (CELLTYPE "stratixgx_ram_register")
    (INSTANCE u6_aaltsyncram_component_aauto_generated_aram_block1a1.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (2602:2602:2602) (2578:2578:2578))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (131:131:131))
      (HOLD d (posedge clk) (34:34:34))
    )
  )
  (CELL
    (CELLTYPE "stratixgx_ram_register")
    (INSTANCE u6_aaltsyncram_component_aauto_generated_aram_block1a1.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (935:935:935) (915:915:915))
        (PORT d[1] (1339:1339:1339) (1312:1312:1312))
        (PORT d[2] (1568:1568:1568) (1542:1542:1542))
        (PORT d[3] (1328:1328:1328) (1302:1302:1302))
        (PORT d[4] (1224:1224:1224) (1177:1177:1177))
        (PORT d[5] (1235:1235:1235) (1187:1187:1187))
        (PORT d[6] (1323:1323:1323) (1317:1317:1317))
        (PORT d[7] (1602:1602:1602) (1566:1566:1566))
        (PORT d[8] (1600:1600:1600) (1578:1578:1578))
        (PORT d[9] (1343:1343:1343) (1339:1339:1339))
        (PORT clk (2602:2602:2602) (2578:2578:2578))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (131:131:131))
      (HOLD d (posedge clk) (34:34:34))
    )
  )
  (CELL
    (CELLTYPE "stratixgx_ram_register")
    (INSTANCE u6_aaltsyncram_component_aauto_generated_aram_block1a1.active_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (2602:2602:2602) (2602:2602:2602))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixgx_ram_pulse_generator")
    (INSTANCE u6_aaltsyncram_component_aauto_generated_aram_block1a1.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (3022:3022:3022) (2998:2998:2998))
        (IOPATH (posedge clk) pulse (0:0:0) (1943:1943:1943))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixgx_ram_register")
    (INSTANCE u6_aaltsyncram_component_aauto_generated_aram_block1a1.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (2590:2590:2590) (2566:2566:2566))
        (IOPATH (posedge clk) q (491:491:491) (491:491:491))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (131:131:131))
      (HOLD d (posedge clk) (34:34:34))
    )
  )
  (CELL
    (CELLTYPE "stratixgx_ram_register")
    (INSTANCE u6_aaltsyncram_component_aauto_generated_aram_block1a3.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (2614:2614:2614) (2592:2592:2592))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (131:131:131))
      (HOLD d (posedge clk) (34:34:34))
    )
  )
  (CELL
    (CELLTYPE "stratixgx_ram_register")
    (INSTANCE u6_aaltsyncram_component_aauto_generated_aram_block1a3.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1330:1330:1330) (1318:1318:1318))
        (PORT d[1] (1324:1324:1324) (1303:1303:1303))
        (PORT d[2] (1550:1550:1550) (1535:1535:1535))
        (PORT d[3] (1342:1342:1342) (1312:1312:1312))
        (PORT d[4] (1330:1330:1330) (1320:1320:1320))
        (PORT d[5] (1615:1615:1615) (1579:1579:1579))
        (PORT d[6] (1345:1345:1345) (1342:1342:1342))
        (PORT d[7] (911:911:911) (900:900:900))
        (PORT d[8] (1564:1564:1564) (1546:1546:1546))
        (PORT d[9] (1317:1317:1317) (1315:1315:1315))
        (PORT clk (2614:2614:2614) (2592:2592:2592))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (131:131:131))
      (HOLD d (posedge clk) (34:34:34))
    )
  )
  (CELL
    (CELLTYPE "stratixgx_ram_register")
    (INSTANCE u6_aaltsyncram_component_aauto_generated_aram_block1a3.active_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (2614:2614:2614) (2614:2614:2614))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixgx_ram_pulse_generator")
    (INSTANCE u6_aaltsyncram_component_aauto_generated_aram_block1a3.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (3034:3034:3034) (3012:3012:3012))
        (IOPATH (posedge clk) pulse (0:0:0) (1943:1943:1943))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixgx_ram_register")
    (INSTANCE u6_aaltsyncram_component_aauto_generated_aram_block1a3.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (2602:2602:2602) (2580:2580:2580))
        (IOPATH (posedge clk) q (491:491:491) (491:491:491))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (131:131:131))
      (HOLD d (posedge clk) (34:34:34))
    )
  )
  (CELL
    (CELLTYPE "stratixgx_asynch_io")
    (INSTANCE FOUT_a0_a_aI.inst1)
    (DELAY
      (ABSOLUTE
        (PORT datain (1303:1303:1303) (1396:1396:1396))
        (IOPATH datain padio (2404:2404:2404) (2404:2404:2404))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixgx_asynch_io")
    (INSTANCE FOUT_a1_a_aI.inst1)
    (DELAY
      (ABSOLUTE
        (PORT datain (1338:1338:1338) (1419:1419:1419))
        (IOPATH datain padio (2404:2404:2404) (2404:2404:2404))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixgx_asynch_io")
    (INSTANCE FOUT_a2_a_aI.inst1)
    (DELAY
      (ABSOLUTE
        (PORT datain (1344:1344:1344) (1420:1420:1420))
        (IOPATH datain padio (2404:2404:2404) (2404:2404:2404))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixgx_asynch_io")
    (INSTANCE FOUT_a3_a_aI.inst1)
    (DELAY
      (ABSOLUTE
        (PORT datain (1229:1229:1229) (1350:1350:1350))
        (IOPATH datain padio (2404:2404:2404) (2404:2404:2404))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixgx_asynch_io")
    (INSTANCE FOUT_a4_a_aI.inst1)
    (DELAY
      (ABSOLUTE
        (PORT datain (1324:1324:1324) (1408:1408:1408))
        (IOPATH datain padio (2404:2404:2404) (2404:2404:2404))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixgx_asynch_io")
    (INSTANCE FOUT_a5_a_aI.inst1)
    (DELAY
      (ABSOLUTE
        (PORT datain (1057:1057:1057) (1140:1140:1140))
        (IOPATH datain padio (2404:2404:2404) (2404:2404:2404))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixgx_asynch_io")
    (INSTANCE FOUT_a6_a_aI.inst1)
    (DELAY
      (ABSOLUTE
        (PORT datain (1260:1260:1260) (1367:1367:1367))
        (IOPATH datain padio (2687:2687:2687) (2687:2687:2687))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixgx_asynch_io")
    (INSTANCE FOUT_a7_a_aI.inst1)
    (DELAY
      (ABSOLUTE
        (PORT datain (1056:1056:1056) (1139:1139:1139))
        (IOPATH datain padio (2404:2404:2404) (2404:2404:2404))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixgx_asynch_io")
    (INSTANCE FOUT_a8_a_aI.inst1)
    (DELAY
      (ABSOLUTE
        (PORT datain (1311:1311:1311) (1401:1401:1401))
        (IOPATH datain padio (2687:2687:2687) (2687:2687:2687))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixgx_asynch_io")
    (INSTANCE FOUT_a9_a_aI.inst1)
    (DELAY
      (ABSOLUTE
        (PORT datain (1307:1307:1307) (1397:1397:1397))
        (IOPATH datain padio (2404:2404:2404) (2404:2404:2404))
      )
    )
  )
)