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📁 dds实现波形的生成
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123 
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_FWORD(9),
	combout => FWORD_a9_a_acombout);

u2_aDOUT_a9_a_aI : stratixgx_lcell
-- Equation(s):
-- u2_aDOUT_a9_a = DFFEAS(FWORD_a9_a_acombout $ u2_aDOUT_a9_a $ (!u2_aDOUT_a4_a_a87 & u2_aDOUT_a8_a_a103) # (u2_aDOUT_a4_a_a87 & u2_aDOUT_a8_a_a103COUT1_118), GLOBAL(CLK_acombout), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "9696",
	cin_used => "true",
	cin0_used => "true",
	cin1_used => "true",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	dataa => FWORD_a9_a_acombout,
	datab => u2_aDOUT_a9_a,
	aclr => GND,
	cin => u2_aDOUT_a4_a_a87,
	cin0 => u2_aDOUT_a8_a_a103,
	cin1 => u2_aDOUT_a8_a_a103COUT1_118,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => u2_aDOUT_a9_a);

u3_aDOUT_a9_a_aI : stratixgx_lcell
-- Equation(s):
-- u3_aDOUT_a9_a = DFFEAS(GND, GLOBAL(CLK_acombout), VCC, , , u2_aDOUT_a9_a, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0000",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	datac => u2_aDOUT_a9_a,
	aclr => GND,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => u3_aDOUT_a9_a);

u6_aaltsyncram_component_aauto_generated_aram_block1a0 : stratixgx_ram_block
-- pragma translate_off
GENERIC MAP (
	mem_init1 => X"43223233232332323323223232232332323323223211010010110100101101001001011011010010010010032232232232232232232233233223223323322332332233223322110011001100110011000110011100111001110001110001110001111000111100000111100000111111000000001111111111000000000000000000000000000001111111111000000001111110000011110000011110001111000111000111000111001110011100110001100110011001100112233223322332332233233223223323322322322322322322322300100100100101101101001001011010010110100101123223233232332322323223233232332323323223",
	mem_init0 => X"45445455454554545545445454454554545545445677676676776766767767667667677677676676676674454454454454454454454455455445445545544554554455445566776677667766776677666776677766777667776667776667776667777666777766666777766666777777666666667777777777000000000000000000000000000007777777777666666667777776666677776666677776667777666777666777666777667776677766776667766776677667766776655445544554554455455445445545544544544544544544544544766766766767767767667667677676676776766767765445455454554544545445455454554545545445",
	operation_mode => "rom",
	ram_block_type => "M4K",
	logical_ram_name => "lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ALTSYNCRAM",
	init_file => "sinsin.mif",
	init_file_layout => "port_a",
	data_interleave_width_in_bits => 1,
	data_interleave_offset_in_bits => 1,
	port_a_write_enable_clock => "none",
	port_a_byte_enable_clock => "none",
	port_a_address_width => 10,
	port_b_address_width => 10,
	port_a_logical_ram_depth => 1024,
	port_a_logical_ram_width => 10,
	port_a_data_in_clear => "none",
	port_a_address_clear => "none",
	port_a_write_enable_clear => "none",
	port_a_byte_enable_clear => "none",
	port_a_data_out_clock => "clock0",
	port_a_data_out_clear => "none",
	port_a_first_address => 0,
	port_a_last_address => 1023,
	port_a_first_bit_number => 0,
	port_a_data_width => 4,
	port_b_data_width => 4)
-- pragma translate_on
PORT MAP (
	clk0 => CLK_acombout,
	portaaddr => u6_aaltsyncram_component_aauto_generated_aram_block1a0_PORTAADDR_bus,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	portadataout => u6_aaltsyncram_component_aauto_generated_aram_block1a0_PORTADATAOUT_bus);

u6_aaltsyncram_component_aauto_generated_aram_block1a1 : stratixgx_ram_block
-- pragma translate_off
GENERIC MAP (
	mem_init1 => X"07776655544777665554443322211000332221110077766655444777665554443332211100033322211100077766655544477766655544433332221110000333222211110000777766665555444477777666655555444443333332222221111110000000333333333222222222111111111111110000000000000000000000000000000000000000000000000111111111111112222222223333333330000000111111222222333333444445555566667777744445555666677770000111122223330000111222333344455566677744455566677700011122233300011122333444555667774445566677700111222330001122233444555667774455566777",
	mem_init0 => X"00111222330001122233444556667774455566777000112223330011122233444555666777445556667770001112223330001112223333444555666677744445556666777700001111222233330000111112222233333444445555556666667777777444444455555555566666666666777777777777777777888888888888888888888888888887777777777777777776666666666655555555544444447777777666666555555444443333322222111110000333322221111000077776666555444477766665554443333222111000333222111000777666555447776665554443322211100333222110007776655544777666554443322211000332221110",
	operation_mode => "rom",
	ram_block_type => "M4K",
	logical_ram_name => "lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ALTSYNCRAM",
	init_file => "sinsin.mif",
	init_file_layout => "port_a",
	data_interleave_width_in_bits => 1,
	data_interleave_offset_in_bits => 1,
	port_a_write_enable_clock => "none",
	port_a_byte_enable_clock => "none",
	port_a_address_width => 10,
	port_b_address_width => 10,
	port_a_logical_ram_depth => 1024,
	port_a_logical_ram_width => 10,
	port_a_data_in_clear => "none",
	port_a_address_clear => "none",
	port_a_write_enable_clear => "none",
	port_a_byte_enable_clear => "none",
	port_a_data_out_clock => "clock0",
	port_a_data_out_clear => "none",
	port_a_first_address => 0,
	port_a_last_address => 1023,
	port_a_first_bit_number => 1,
	port_a_data_width => 4,
	port_b_data_width => 4)
-- pragma translate_on
PORT MAP (
	clk0 => CLK_acombout,
	portaaddr => u6_aaltsyncram_component_aauto_generated_aram_block1a1_PORTAADDR_bus,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	portadataout => u6_aaltsyncram_component_aauto_generated_aram_block1a1_PORTADATAOUT_bus);

u6_aaltsyncram_component_aauto_generated_aram_block1a3 : stratixgx_ram_block
-- pragma translate_off
GENERIC MAP (
	mem_init0 => X"3FFFFEAAAAAFFFFFAAAAAFFFFFEAAAAAFFFFFEAAAAA95555540000015555554000000055555555000000000155555555555500000000000000000000000000000000000000000000000000000000155555555555500000000015555555400000005555555000000555555AAAAAAFFFFFEAAAAAFFFFFEAAAABFFFFEAAAAAFFFFF0000055555000001555540000055555000000555556AAAAABFFFFFFAAAAAABFFFFFFFAAAAAAAAFFFFFFFFFEAAAAAAAAAAABFFFFFFFFFFFFFFFFFFFFFF000000000000003FFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAFFFFFFFFFEAAAAAAABFFFFFFFAAAAAABFFFFFFAAAAAA555554000001555540000055555000001555540000",
	operation_mode => "rom",
	ram_block_type => "M4K",
	logical_ram_name => "lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ALTSYNCRAM",
	init_file => "sinsin.mif",
	init_file_layout => "port_a",
	data_interleave_width_in_bits => 1,
	data_interleave_offset_in_bits => 1,
	port_a_write_enable_clock => "none",
	port_a_byte_enable_clock => "none",
	port_a_address_width => 10,
	port_b_address_width => 10,
	port_a_logical_ram_depth => 1024,
	port_a_logical_ram_width => 10,
	port_a_data_in_clear => "none",
	port_a_address_clear => "none",
	port_a_write_enable_clear => "none",
	port_a_byte_enable_clear => "none",
	port_a_data_out_clock => "clock0",
	port_a_data_out_clear => "none",
	port_a_first_address => 0,
	port_a_last_address => 1023,
	port_a_first_bit_number => 3,
	port_a_data_width => 2,
	port_b_data_width => 2)
-- pragma translate_on
PORT MAP (
	clk0 => CLK_acombout,
	portaaddr => u6_aaltsyncram_component_aauto_generated_aram_block1a3_PORTAADDR_bus,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	portadataout => u6_aaltsyncram_component_aauto_generated_aram_block1a3_PORTADATAOUT_bus);

FOUT_a0_a_aI : stratixgx_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => u6_aaltsyncram_component_aauto_generated_aq_a_a0_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_FOUT(0));

FOUT_a1_a_aI : stratixgx_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => u6_aaltsyncram_component_aauto_generated_aq_a_a1_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_FOUT(1));

FOUT_a2_a_aI : stratixgx_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => u6_aaltsyncram_component_aauto_generated_aq_a_a2_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_FOUT(2));

FOUT_a3_a_aI : stratixgx_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => u6_aaltsyncram_component_aauto_generated_aq_a_a3_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_FOUT(3));

FOUT_a4_a_aI : stratixgx_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => u6_aaltsyncram_component_aauto_generated_aq_a_a4_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_FOUT(4));

FOUT_a5_a_aI : stratixgx_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => u6_aaltsyncram_component_aauto_generated_aq_a_a5_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_FOUT(5));

FOUT_a6_a_aI : stratixgx_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => u6_aaltsyncram_component_aauto_generated_aq_a_a6_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_FOUT(6));

FOUT_a7_a_aI : stratixgx_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => u6_aaltsyncram_component_aauto_generated_aq_a_a7_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_FOUT(7));

FOUT_a8_a_aI : stratixgx_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => u6_aaltsyncram_component_aauto_generated_aq_a_a8_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_FOUT(8));

FOUT_a9_a_aI : stratixgx_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => u6_aaltsyncram_component_aauto_generated_aq_a_a9_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_FOUT(9));
END structure;
123

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